[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20160519113116.GL3205@twins.programming.kicks-ass.net>
Date: Thu, 19 May 2016 13:31:16 +0200
From: Peter Zijlstra <peterz@...radead.org>
To: David Howells <dhowells@...hat.com>
Cc: linux-arch@...r.kernel.org, x86@...nel.org, will.deacon@....com,
linux-kernel@...r.kernel.org, ramana.radhakrishnan@....com,
paulmck@...ux.vnet.ibm.com, dwmw2@...radead.org
Subject: Re: [RFC PATCH 03/15] Provide atomic_t functions implemented with
ISO-C++11 atomics
On Thu, May 19, 2016 at 12:50:00PM +0200, Peter Zijlstra wrote:
> > I suspect that might be quite a stretch.
> >
> > I've opened:
> >
> > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71191
> >
> > to cover this.
>
> Thanks; until such time as this stretch has been made I don't see this
> intrinsic stuff being much use on any of the LL/SC archs.
FWIW, Will and me have been discussing a GCC/LLVM language extension
that would allow generating the insides of LL/SC loops. But neither has
had time to properly write something down yet :/
My latest thinking is something along the lines of:
static __always_inline int __load_locked(int *ptr)
{
int val;
__asm__ __volatile__ ("ldaxr %[val], [%[ptr]]"
: [val] "r" (val)
: [ptr] "m" (*ptr));
return val;
}
static __always_inline bool __store_conditional(int *ptr, int old, int new)
{
int ret;
__asm__ __volatile__ ("stlxr %[ret], %[new], [%[ptr]]"
: [ret] "r" (ret)
: [new] "r" (new),
[ptr] "m" (*ptr));
return ret != 0;
}
bool atomic_add_unless(atomic_t *v, int a, int u)
{
int val, old;
do __special_marker__ {
old = val = __load_locked(&v->counter);
if (val == u)
goto fail;
val += a;
} while (__store_conditional(&v->counter, old, val));
return true;
fail:
return false;
}
Where the __special_marker__ marks the whole { } scope as being the
inside of LL/SC and all variables must be in registers before we start.
If the compiler is not able to guarantee this, it must generate a
compile time error etc..
The __sc takes the @old and @new arguments such that we can implement
this on CAS archs with a regular load and CAS.
Powered by blists - more mailing lists