[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20160519144117.GX3193@twins.programming.kicks-ass.net>
Date: Thu, 19 May 2016 16:41:17 +0200
From: Peter Zijlstra <peterz@...radead.org>
To: "Paul E. McKenney" <paulmck@...ux.vnet.ibm.com>
Cc: David Howells <dhowells@...hat.com>, linux-arch@...r.kernel.org,
x86@...nel.org, will.deacon@....com, linux-kernel@...r.kernel.org,
ramana.radhakrishnan@....com, dwmw2@...radead.org
Subject: Re: [RFC PATCH 03/15] Provide atomic_t functions implemented with
ISO-C++11 atomics
On Thu, May 19, 2016 at 07:22:52AM -0700, Paul E. McKenney wrote:
> Agreed, these sorts of instruction sequences make a lot of sense.
> Of course, if you stuff too many intructions and cache misses between
> the LL and the SC, the SC success probability starts dropping, but short
> seqeunces of non-memory-reference instructions like the above should be
> just fine.
In fact, pretty much every single LL/SC arch I've looked at doesn't
allow _any_ loads or stores inside and will guarantee SC failure (or
worse) if you do.
This immediately disqualifies things like calls/traps/etc.. because
those implicitly issue stores.
Powered by blists - more mailing lists