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Message-Id: <1464066139-22648-1-git-send-email-ykk@rock-chips.com> Date: Tue, 24 May 2016 13:02:19 +0800 From: Yakir Yang <ykk@...k-chips.com> To: David Airlie <airlied@...ux.ie>, Inki Dae <inki.dae@...sung.com>, Mark Yao <yzq@...k-chips.com>, Thierry Reding <treding@...dia.com>, Jingoo Han <jingoohan1@...il.com>, Rob Herring <robh+dt@...nel.org> Cc: Krzysztof Kozlowski <k.kozlowski@...sung.com>, Heiko Stuebner <heiko@...ech.de>, Douglas Anderson <dianders@...omium.org>, Daniel Vetter <daniel.vetter@...ll.ch>, Javier Martinez Canillas <javier@....samsung.com>, emil.l.velikov@...il.com, Dan Carpenter <dan.carpenter@...cle.com>, linux-kernel@...r.kernel.org, dri-devel@...ts.freedesktop.org, linux-samsung-soc@...r.kernel.org, linux-rockchip@...ts.infradead.org, Yakir Yang <ykk@...k-chips.com> Subject: [PATCH v2 03/10] drm/bridge: analogix_dp: correct the register bit define error in ANALOGIX_DP_PLL_REG_1 There're an register define error in ANALOGIX_DP_PLL_REG_1 which introduced by commit bcec20fd5ad6 ("drm: bridge: analogix/dp: add some rk3288 special registers setting"). The PHY PLL input clock source is selected by ANALOGIX_DP_PLL_REG_1 BIT 0, not BIT 1. Signed-off-by: Yakir Yang <ykk@...k-chips.com> --- Changes in v2: None drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h index 337912b..88d56ad 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h @@ -163,8 +163,8 @@ #define HSYNC_POLARITY_CFG (0x1 << 0) /* ANALOGIX_DP_PLL_REG_1 */ -#define REF_CLK_24M (0x1 << 1) -#define REF_CLK_27M (0x0 << 1) +#define REF_CLK_24M (0x1 << 0) +#define REF_CLK_27M (0x0 << 0) /* ANALOGIX_DP_LANE_MAP */ #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6) -- 1.9.1
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