lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Message-Id: <1464113250-15629-4-git-send-email-rob.rice@broadcom.com> Date: Tue, 24 May 2016 14:07:30 -0400 From: Rob Rice <rob.rice@...adcom.com> To: Jassi Brar <jassisinghbrar@...il.com>, Rob Herring <robh+dt@...nel.org>, Pawel Moll <pawel.moll@....com>, Mark Rutland <mark.rutland@....com>, Ian Campbell <ijc+devicetree@...lion.org.uk>, Kumar Gala <galak@...eaurora.org> Cc: devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, bcm-kernel-feedback-list@...adcom.com, linux-kernel@...r.kernel.org, Ray Jui <rjui@...adcom.com>, Scott Branden <sbranden@...adcom.com>, Jon Mason <jonmason@...adcom.com>, Florian Fainelli <f.fainelli@...il.com>, Anup Patel <anup.patel@...adcom.com>, Catalin Marinas <catalin.marinas@....com>, Will Deacon <will.deacon@....com>, Rob Rice <rrice@...adcom.com>, Rob Rice <rob.rice@...adcom.com> Subject: [PATCH 3/3] arm64: dts: Add Broadcom Northstar2 device tree entries for PDC driver. From: Rob Rice <rrice@...adcom.com> Add Broadcom Northstar2 SoC device tree entries for PDC driver. Signed-off-by: Rob Rice <rob.rice@...adcom.com> Reviewed-by: Ray Jui <ray.jui@...adcom.com> Reviewed-by: Scott Branden <scott.branden@...adcom.com> --- arch/arm64/boot/dts/broadcom/ns2.dtsi | 36 +++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi index ec68ec1..ba12702 100644 --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi @@ -191,6 +191,42 @@ #include "ns2-clock.dtsi" + pdc0: iproc-pdc0@...c0000 { + compatible = "brcm,iproc-pdc-mbox"; + reg = <0x612c0000 0x445>; /* PDC FS0 regs */ + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <1>; + brcm,rx-status-len = <32>; + brcm,use-bcm-hdr; + }; + + pdc1: iproc-pdc1@...e0000 { + compatible = "brcm,iproc-pdc-mbox"; + reg = <0x612e0000 0x445>; /* PDC FS1 regs */ + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <1>; + brcm,rx-status-len = <32>; + brcm,use-bcm-hdr; + }; + + pdc2: iproc-pdc2@...00000 { + compatible = "brcm,iproc-pdc-mbox"; + reg = <0x61300000 0x445>; /* PDC FS2 regs */ + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <1>; + brcm,rx-status-len = <32>; + brcm,use-bcm-hdr; + }; + + pdc3: iproc-pdc3@...20000 { + compatible = "brcm,iproc-pdc-mbox"; + reg = <0x61320000 0x445>; /* PDC FS3 regs */ + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <1>; + brcm,rx-status-len = <32>; + brcm,use-bcm-hdr; + }; + dma0: dma@...60000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x61360000 0x1000>; -- 2.1.0
Powered by blists - more mailing lists