linux-kernel - Re: [PATCH] PCI/ASPM: fix reverse ASPM L0s assignment of upstream and downstream

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Message-ID: <5745EC95.1020506@codeaurora.org>
Date:	Wed, 25 May 2016 14:19:01 -0400
From:	Sinan Kaya <okaya@...eaurora.org>
To:	Bjorn Helgaas <helgaas@...nel.org>
Cc:	Ocean HY1 He <hehy1@...ovo.com>,
	"bhelgaas@...gle.com" <bhelgaas@...gle.com>,
	"wangyijing@...wei.com" <wangyijing@...wei.com>,
	"luto@...nel.org" <luto@...nel.org>,
	"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"prarit@...hat.com" <prarit@...hat.com>,
	"jcm@...hat.com" <jcm@...hat.com>,
	Nagananda Chumbalkar <nchumbalkar@...ovo.com>
Subject: Re: [PATCH] PCI/ASPM: fix reverse ASPM L0s assignment of upstream and
 downstream

On 5/25/2016 1:50 PM, Bjorn Helgaas wrote:
>> > You are saying that it is OK to enable L0s on just one side of the
>> > link as long as both sides support L0s. 
> I'm not sure what you mean by the link parameters not being
> compatible, but I think it is legal to enable L0s on only one
> direction.

I'm talking about L0s acceptable and entry latency times used to
determine when L0s can be enabled.

> 
>> > This part is a little bit misleading. I had HW people telling me
>> > that both sides need to enable L0s at about the same time.
> I don't remember seeing anything like that in the spec.  Do they have
> a pointer?  "At about the same time" is too hand-wavey to be useful to
> software.
> 

OK. Let me do some more push back. I wanted to understand the OS
behavior and its reasoning.

Your answers are sufficient.

-- 
Sinan Kaya
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project