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Message-ID: <7878987.CKGkxk3Y7s@phil>
Date: Fri, 27 May 2016 01:17:27 +0200
From: Heiko Stuebner <heiko@...ech.de>
To: Xing Zheng <zhengxing@...k-chips.com>
Cc: linux-rockchip@...ts.infradead.org, dianders@...omium.org,
huangtao@...k-chips.com, elaine.zhang@...k-chips.com,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...eaurora.org>, linux-clk@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] clk: rockchip: add a dummy clock for the watchdog pclk on rk3399
Am Mittwoch, 25. Mai 2016, 16:51:56 schrieb Xing Zheng:
> Like rk3288, the pclk supplying the watchdog is controlled via the
> SGRF register area. Additionally the SGRF isn't even writable in
> every boot mode.
>
> But still the clock control is available and in the future someone
> might want to use it. Therefore define a simple clock for the time
> being so that the watchdog driver can read its rate.
>
> Signed-off-by: Xing Zheng <zhengxing@...k-chips.com>
applied for 4.8
Thanks
Heiko
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