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Message-ID: <574BFD61.60101@synopsys.com>
Date:	Mon, 30 May 2016 09:44:17 +0100
From:	Jose Abreu <Jose.Abreu@...opsys.com>
To:	Jose Abreu <Jose.Abreu@...opsys.com>,
	"airlied@...ux.ie" <airlied@...ux.ie>,
	"dri-devel@...ts.freedesktop.org" <dri-devel@...ts.freedesktop.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	<Alexey.Brodkin@...opsys.com>
Subject: Re: DRM DMA Engine

Hi Daniel,

Thanks for your answer.

On 26-05-2016 09:06, Daniel Vetter wrote:
> On Wed, May 25, 2016 at 04:46:15PM +0100, Jose Abreu wrote:
>> Hi all,
>>
>> Currently I am trying to develop a DRM driver that will use
>> Xilinx VDMA to transfer video data to a HDMI TX Phy and I am
>> facing a difficulty regarding the understanding of the DRM DMA
>> Engine. I looked at several sources and at the DRM core source
>> but the flow of creating and interfacing with the DMA controller
>> is still not clear to me.
>>
>> At DRI web page the X server is mentioned. Does it mean that the
>> channel creation and handling is done by the X server? If so,
>> what is the DRM driver responsible to do then and what exactly
>> does the DRM core do? As I am using Xilinx VDMA do you foresee
>> any special implementation details?
>>
>> Just for reference here is the description of the Xilinx VDMA:
>> "The Advanced eXtensible Interface Video Direct Memory Access
>> (AXI VDMA) core is a soft Xilinx Intellectual Property (IP) core
>> providing high-bandwidth direct memory access between memory and
>> AXI4-Stream video type target peripherals including  peripherals
>> which support AXI4-Stream Video Protocol." The driver is
>> available at "drivers/dma/xilinx/xilinx_vdma.c".
>>
>> Another important point: I am using PCI Express connected to a
>> FPGA which has all the necessary components (Xilinx VDMA, I2S,
>> ...) and the HDMI TX Phy.
>>
>> Looking forward to you help.
> If your dma engine is just for HDMI display, forget all the stuff you find
> about DRI and X server on the various wikis. That's for opengl rendering.
>
> The only thing you need is a kernel-modesetting driver, and nowadays those
> are written using the atomic modeset framework. There's plenty of
> introductory talks and stuff all over the web (I suggest the latest
> version of Laurent Pinchart's talk as a good starting point).
> -Daniel

I watched the talk of Laurent and I already have a simple KMS
driver with an encoder (which is bridge dw-hdmi), a connector and
a crtc. My doubt now is how do I setup the video path so that
video samples are sent using the Xilinx VDMA to our hdmi phy.

Sorry if I am making some mistake (I am quite new to DRM and DMA)
but here is my thoughts:
    - A DMA channel or some kind of mapping must be done so that
the DRM driver knows where to send samples;
    - The Xilinx VDMA driver must be instantiated (which I am
already doing);
    - Some kind of association between the DRM DMA engine and
Xilinx VDMA must be done;
    - A callback should exist that is called on each frame and
updates the data that is sent to Xilinx VDMA.

Does this looks okay to you or am I missing something? I still
haven't figured out how should I associate the VDMA to the DRM
DMA engine and how should I map the DMA to the DRM driver.

Can you give me some help or refer me to someone who can? Also,
is there a DRM driver that uses a similar architecture?

>> Best regards,
>> Jose Miguel Abreu
>> _______________________________________________
>> dri-devel mailing list
>> dri-devel@...ts.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/dri-devel

Best regards,
Jose Miguel Abreu

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