linux-kernel - Re: [PATCH 10/17] pinctrl: uniphier: introduce capability flag

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Message-ID: <CACRpkdaGqCfNYcqNbWwLzcBngqrPX23JDOyQfeeBO+5ngxd1gQ@mail.gmail.com>
Date:	Tue, 31 May 2016 12:49:16 +0200
From:	Linus Walleij <linus.walleij@...aro.org>
To:	Masahiro Yamada <yamada.masahiro@...ionext.com>
Cc:	"linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 10/17] pinctrl: uniphier: introduce capability flag

On Tue, May 31, 2016 at 10:05 AM, Masahiro Yamada
<yamada.masahiro@...ionext.com> wrote:

> The core part of the UniPhier pinctrl driver needs to support a new
> capability for upcoming UniPhier ARMv8 SoCs.  This sometimes happens
> because pinctrl drivers include really SoC-specific stuff.
>
> This commit intends to tidy up SoC-specific parameters of the existing
> drivers before adding the new one.  Having just one flag would be
> better than adding a new struct member every time a new SoC-specific
> capability comes up.
>
> At this time, there is one flag, UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE.
> This capability (I'd say rather quirk) was added for PH1-Pro4 and
> PH1-Pro5 as requirement from a customer.  For those SoCs, one pin-mux
> setting is controlled by the combination of two separate registers; the
> LSB bits at register offset (8 * N) and the MSB bits at (8 * N + 4).
> Because it is impossible to update two separate registers atomically,
> the LOAD_PINCTRL register should be set in order to make the pin-mux
> settings really effective.
>
> Signed-off-by: Masahiro Yamada <yamada.masahiro@...ionext.com>

Patch applied.

Yours,
Linus Walleij