linux-kernel - Re: [PATCH 2/3] perf/x86/intel: fix for MSR_LAST_BRANCH_FROM

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Date:	Fri, 3 Jun 2016 11:21:15 +0200
From:	Peter Zijlstra <peterz@...radead.org>
To:	David Carrillo-Cisneros <davidcc@...gle.com>
Cc:	linux-kernel@...r.kernel.org, "x86@...nel.org" <x86@...nel.org>,
	Ingo Molnar <mingo@...hat.com>,
	"Yan, Zheng" <zheng.z.yan@...el.com>,
	Andi Kleen <ak@...ux.intel.com>,
	Kan Liang <kan.liang@...el.com>,
	Stephane Eranian <eranian@...gle.com>
Subject: Re: [PATCH 2/3] perf/x86/intel: fix for MSR_LAST_BRANCH_FROM_x quirk
 when no TSX

On Thu, Jun 02, 2016 at 05:00:19PM +0000, David Carrillo-Cisneros wrote:

> LBR_FROM_FLAG_MISPRED is at bit 63 so the bitshift wouldnt work . But I can
> clean the bits unconditionally of the value, just as you said for the read
> case.

Argh, missed that. Ok, something like so then:

#define LBR_FROM_SIGN_MASK	(BIT_ULL(61) | BIT_ULL(62))

	/*
	 * Sign extend into bits 61,62 while preserving bit 63.
	 *
	 * This works because bits 59 and 60 are guaranteed to be sign
	 * bits themselves.
	 */
	val = (val & ~LBR_FROM_SIGN_MASK) | ((val << 2) & LBR_FROM_SIGN_MASK);

A superscalar core can evaluate the left and right hand parts of the
logical or concurrently.

I've not generated the code so see what GCC does with the 64bit
literals, ideally it would generate code using 32bit literals and only
operate on the high word, but who knows if its smart enough for that.

See also:

https://graphics.stanford.edu/~seander/bithacks.html#ConditionalSetOrClearBitsWithoutBranching