linux-kernel - [tip:perf/core] perf/x86/intel: Change offcore response masks for Knights Landing

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [day] [month] [year] [list]

Message-ID: <tip-9c489fce7a4a46c8a408e16e126bf3225401c7b5@git.kernel.org>
Date:	Fri, 3 Jun 2016 03:51:04 -0700
From:	tip-bot for Lukasz Odzioba <tipbot@...or.com>
To:	linux-tip-commits@...r.kernel.org
Cc:	eranian@...gle.com, ak@...ux.intel.com, mingo@...nel.org,
	alexander.shishkin@...ux.intel.com, torvalds@...ux-foundation.org,
	peterz@...radead.org, tglx@...utronix.de,
	linux-kernel@...r.kernel.org, jolsa@...hat.com,
	vincent.weaver@...ne.edu, lukasz.odzioba@...el.com,
	acme@...hat.com, hpa@...or.com
Subject: [tip:perf/core] perf/x86/intel: Change offcore response masks for
 Knights Landing

Commit-ID:  9c489fce7a4a46c8a408e16e126bf3225401c7b5
Gitweb:     http://git.kernel.org/tip/9c489fce7a4a46c8a408e16e126bf3225401c7b5
Author:     Lukasz Odzioba <lukasz.odzioba@...el.com>
AuthorDate: Mon, 16 May 2016 23:16:59 +0200
Committer:  Ingo Molnar <mingo@...nel.org>
CommitDate: Fri, 3 Jun 2016 09:40:17 +0200

perf/x86/intel: Change offcore response masks for Knights Landing

Due to change in register definition we need to update OCR mask:

MSR_OFFCORE_RESP0 reserved bits: 3,4,18,29,30,33,34, 8,11,14
MSR_OFFCORE_RESP1 reserved bits: 3,4,18,29,30,33,34, 38

Reported-by: Andi Kleen <ak@...ux.intel.com>
Signed-off-by: Lukasz Odzioba <lukasz.odzioba@...el.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@...radead.org>
Cc: Alexander Shishkin <alexander.shishkin@...ux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@...hat.com>
Cc: Jiri Olsa <jolsa@...hat.com>
Cc: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Stephane Eranian <eranian@...gle.com>
Cc: Thomas Gleixner <tglx@...utronix.de>
Cc: Vince Weaver <vincent.weaver@...ne.edu>
Cc: akpm@...ux-foundation.org
Cc: hpa@...or.com
Cc: kan.liang@...el.com
Cc: lukasz.anaczkowski@...el.com
Cc: zheng.z.yan@...el.com
Link: http://lkml.kernel.org/r/1463433419-16893-1-git-send-email-lukasz.odzioba@intel.com
Signed-off-by: Ingo Molnar <mingo@...nel.org>
---
 arch/x86/events/intel/core.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index ad08caf..0941f84 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -186,10 +186,8 @@ static struct event_constraint intel_skl_event_constraints[] = {
 };
 
 static struct extra_reg intel_knl_extra_regs[] __read_mostly = {
-	INTEL_UEVENT_EXTRA_REG(0x01b7,
-			       MSR_OFFCORE_RSP_0, 0x7f9ffbffffull, RSP_0),
-	INTEL_UEVENT_EXTRA_REG(0x02b7,
-			       MSR_OFFCORE_RSP_1, 0x3f9ffbffffull, RSP_1),
+	INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0),
+	INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1),
 	EVENT_EXTRA_END
 };