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Message-Id: <1464966911-18949-2-git-send-email-zyw@rock-chips.com>
Date: Fri, 3 Jun 2016 23:15:08 +0800
From: Chris Zhong <zyw@...k-chips.com>
To: dianders@...omium.org, tfiga@...omium.org, heiko@...ech.de,
yzq@...k-chips.com
Cc: linux-rockchip@...ts.infradead.org,
Chris Zhong <zyw@...k-chips.com>,
Rob Herring <robh+dt@...nel.org>,
Pawel Moll <pawel.moll@....com>,
Mark Rutland <mark.rutland@....com>,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
Kumar Gala <galak@...eaurora.org>, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: [v1 PATCH 1/4] Documentation: bindings: add dt doc for Rockchip USB Type-C PHY
This patch adds a binding that describes the Rockchip USB Type-C PHY
for rk3399
Signed-off-by: Chris Zhong <zyw@...k-chips.com>
---
Changes in v1:
- add extcon node description
- move the registers in phy driver
- remove the suffix of reset
.../devicetree/bindings/phy/phy-rockchip-typec.txt | 46 ++++++++++++++++++++++
1 file changed, 46 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
new file mode 100644
index 0000000..964e0f7
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
@@ -0,0 +1,46 @@
+* ROCKCHIP type-c PHY
+---------------------
+
+Required properties:
+ - compatible: should be "rockchip,rk3399-typec-phy0" or
+ "rockchip,rk3399-typec-phy1"
+ - reg : Address and length of the usb phy control register set
+ - rockchip,grf : phandle to the syscon managing the "general
+ register files"
+ - clocks : phandle + clock specifier for the phy clocks
+ - clock-names: string, clock name, must be "tcpdcore", "tcpdphy_ref";
+ - resets : a list of phandle + reset specifier pairs
+ - reset-names : string reset name, must be:
+ "tcphy", "tcphy_pipe", "uphy_tcphy"
+ - #phy-cells: Must be 0. See ./phy-bindings.txt for details.
+ - extcon: extcon specifier for the Power Delivery
+
+Example:
+ tcphy0: phy@...c0000 {
+ compatible = "rockchip,rk3399-typec-phy0";
+ reg = <0x0 0xff7c0000 0x0 0x40000>;
+ #phy-cells = <0>;
+ extcon = <&fusb1>;
+ rockchip,grf = <&grf>;
+ clocks = <&cru SCLK_UPHY0_TCPDCORE>,
+ <&cru SCLK_UPHY0_TCPDPHY_REF>;
+ clock-names = "tcpdcore", "tcpdphy_ref";
+ resets = <&cru SRST_UPHY0>,
+ <&cru SRST_UPHY0_PIPE_L00>,
+ <&cru SRST_P_UPHY0_TCPHY>;
+ reset-names = "tcphy", "tcphy_pipe", "uphy_tcphy";
+ };
+
+ tcphy1: phy@...00000 {
+ compatible = "rockchip,rk3399-typec-phy1";
+ reg = <0x0 0xff800000 0x0 0x40000>;
+ #phy-cells = <0>;
+ rockchip,grf = <&grf>;
+ clocks = <&cru SCLK_UPHY1_TCPDCORE>,
+ <&cru SCLK_UPHY1_TCPDPHY_REF>;
+ clock-names = "tcpdcore", "tcpdphy_ref";
+ resets = <&cru SRST_UPHY1>,
+ <&cru SRST_UPHY1_PIPE_L00>,
+ <&cru SRST_P_UPHY1_TCPHY>;
+ reset-names = "tcphy", "tcphy_pipe", "uphy_tcphy";
+ };
--
2.6.3
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