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Date: Mon, 6 Jun 2016 18:29:45 +0100 From: Mark Rutland <mark.rutland@....com> To: Tai Tri Nguyen <ttnguyen@....com> Cc: Rob Herring <robh@...nel.org>, Will Deacon <will.deacon@....com>, catalin.marinas@....com, linux-kernel@...r.kernel.org, devicetree@...r.kernel.org, linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>, patches <patches@....com> Subject: Re: [PATCH v2 2/4] Documentation: Add documentation for APM X-Gene SoC PMU DTS binding On Tue, May 31, 2016 at 06:25:56PM -0700, Tai Tri Nguyen wrote: > Hi Mark, [...] > I'm facing a problem after removing the index for MCU and MC sub-nodes. > The MCUs and MCs aren't always enabled depending on how DRAM DIMMs are > installed on the system. > I still need a way to associate the MCU with its indicator bit in the > enable mask retrieved from CSR. Ah, I see. Can you elaborate on how the indicator bits are laid out? From the example binding, I see multiple nodes with the same index property, so I'm a little confused. I guess that there's a CSR per class of node (e.g. all MCBs in one CSR register)? Or do several nodes share the same bit? Is there a single CSR register? Are there several? Is that bit index used in other registers? > For MC and MCB nodes only, can I introduce an "enable-mask" field? > For example: > " > pmucmcb@...10000 { > compatible = "apm,xgene-pmu-mcb"; > reg = <0x0 0x7e710000 0x0 0x1000>; > enable-mask = <0x00000001>; > }; > > pmucmcb@...30000 { > compatible = "apm,xgene-pmu-mcb"; > reg = <0x0 0x7e730000 0x0 0x1000>; > enable-mask = <0x00000002>; > }; > " > Or can you please give a suggestion how I can fix it? Assuming it's always a single bit, a *-bit-index property may be fine, and probably preferable. I'm a little confused, so I'd like to understand how it's used. Thanks, Mark.
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