linux-kernel - [RFC PATCH 03/15] clk: samsung: exynos4: fixup reg access on be

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Message-Id: <20160608183110.13851-4-matthew@mattleach.net>
Date:	Wed,  8 Jun 2016 19:30:58 +0100
From:	Matthew Leach <matthew@...tleach.net>
To:	Krzysztof Kozlowski <k.kozlowski@...sung.com>,
	Ben Dooks <ben.dooks@...ethink.co.uk>
Cc:	linux-samsung-soc@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
	Matthew Leach <matthew@...tleach.net>,
	Sylwester Nawrocki <s.nawrocki@...sung.com>,
	Tomasz Figa <tomasz.figa@...il.com>,
	Michael Turquette <mturquette@...libre.com>,
	Stephen Boyd <sboyd@...eaurora.org>,
	Kukjin Kim <kgene@...nel.org>, linux-clk@...r.kernel.org
Subject: [RFC PATCH 03/15] clk: samsung: exynos4: fixup reg access on be

Use the byte-order aware big endian accessors, allowing for kernels
running under big-endian.

Signed-off-by: Matthew Leach <matthew@...tleach.net>
---
CC: Sylwester Nawrocki <s.nawrocki@...sung.com>
CC: Tomasz Figa <tomasz.figa@...il.com>
CC: Michael Turquette <mturquette@...libre.com>
CC: Stephen Boyd <sboyd@...eaurora.org>
CC: Kukjin Kim <kgene@...nel.org>
CC: Krzysztof Kozlowski <k.kozlowski@...sung.com>
CC: linux-samsung-soc@...r.kernel.org
CC: linux-clk@...r.kernel.org
CC: linux-arm-kernel@...ts.infradead.org
CC: linux-kernel@...r.kernel.org
---
 drivers/clk/samsung/clk-exynos4.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 7b3d0f9..35a977d 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -1375,12 +1375,12 @@ static void __init exynos4x12_core_down_clock(void)
 	if (num_possible_cpus() == 4)
 		tmp |= PWR_CTRL1_USE_CORE3_WFE | PWR_CTRL1_USE_CORE2_WFE |
 		       PWR_CTRL1_USE_CORE3_WFI | PWR_CTRL1_USE_CORE2_WFI;
-	__raw_writel(tmp, reg_base + PWR_CTRL1);
+	writel_relaxed(tmp, reg_base + PWR_CTRL1);
 
 	/*
 	 * Disable the clock up feature in case it was enabled by bootloader.
 	 */
-	__raw_writel(0x0, reg_base + E4X12_PWR_CTRL2);
+	writel_relaxed(0x0, reg_base + E4X12_PWR_CTRL2);
 }
 
 #define E4210_CPU_DIV0(apll, pclk_dbg, atb, periph, corem1, corem0)	\
-- 
2.8.3