lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:	Wed, 8 Jun 2016 22:51:56 +0300
From:	Aaro Koskinen <aaro.koskinen@....fi>
To:	Rob Herring <robh@...nel.org>
Cc:	David Daney <ddaney.cavm@...il.com>, devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH] Documentation/devicetree: document cavium-pip
 rx-delay/tx-delay properties

Hi,

On Wed, Jun 08, 2016 at 02:18:42PM -0500, Rob Herring wrote:
> On Sun, Jun 05, 2016 at 01:24:02AM +0300, Aaro Koskinen wrote:
> > Document cavium-pip rx-delay/tx-delay properties. Currently the board
> > specific values need to be hardcoded in the platform code, which we
> > want to avoid when moving to DT-only booting.
> > 
> > Signed-off-by: Aaro Koskinen <aaro.koskinen@....fi>
> > ---
> >  Documentation/devicetree/bindings/net/cavium-pip.txt | 4 ++++
> >  1 file changed, 4 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/net/cavium-pip.txt b/Documentation/devicetree/bindings/net/cavium-pip.txt
> > index 7dbd158..edbf411 100644
> > --- a/Documentation/devicetree/bindings/net/cavium-pip.txt
> > +++ b/Documentation/devicetree/bindings/net/cavium-pip.txt
> > @@ -37,6 +37,10 @@ Properties for PIP port which is a child the PIP interface:
> >  
> >  - phy-handle: Optional, see ethernet.txt file in the same directory.
> >  
> > +- rx-delay: Delay value for RGMII receive clock. Optional. Disabled if 0.
> > +
> > +- tx-delay: Delay value for RGMII transmit clock. Optional. Disabled if 0.
> 
> What are the units? Use standard unit suffix if in ns, us, etc.

This is a raw register value, and the mapping to actual delay varies
depending on HW, AFAIK. 

A.

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ