linux-kernel - Re: [PATCH 1/1] perf/x86/intel: Add extended event constraints for Knights Landing

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20160608064800.GN30154@twins.programming.kicks-ass.net>
Date:	Wed, 8 Jun 2016 08:48:00 +0200
From:	Peter Zijlstra <peterz@...radead.org>
To:	Lukasz Odzioba <lukasz.odzioba@...el.com>
Cc:	linux-kernel@...r.kernel.org, x86@...nel.org, tglx@...utronix.de,
	mingo@...hat.com, hpa@...or.com, ak@...ux.intel.com,
	kan.liang@...el.com, akpm@...ux-foundation.org, eranian@...gle.com,
	acme@...nel.org, alexander.shishkin@...ux.intel.com, bp@...e.de,
	lukasz.anaczkowski@...el.com
Subject: Re: [PATCH 1/1] perf/x86/intel: Add extended event constraints for
 Knights Landing

On Wed, Jun 08, 2016 at 06:02:16AM +0200, Lukasz Odzioba wrote:
> For Knights Landing processor we need to filter OFFCORE_RESPONSE
> events by config1 parameter to make sure that it will end up in
> an appropriate PMC to meet specification.
> 
> On Knights Landing:
> MSR_OFFCORE_RSP_1 bits 8, 11, 14 can be used only on PMC1
> MSR_OFFCORE_RSP_0 bit 38 can be used only on PMC0
> 
> This patch introduces INTEL_EEVENT_CONSTRAINT where third parameter
> specifies extended config bits allowed only on given PMCs.
> 

How does this work in the light of intel_alt_er() ?