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Message-Id: <1465370708-23619-1-git-send-email-shawn.lin@rock-chips.com>
Date: Wed, 8 Jun 2016 15:25:08 +0800
From: Shawn Lin <shawn.lin@...k-chips.com>
To: Kishon Vijay Abraham I <kishon@...com>
Cc: linux-kernel@...r.kernel.org, linux-rockchip@...ts.infradead.org,
Heiko Stuebner <heiko@...ech.de>,
Doug Anderson <dianders@...omium.org>,
Wenrui Li <wenrui.li@...k-chips.com>,
Rob Herring <robh+dt@...nel.org>, devicetree@...r.kernel.org,
Shawn Lin <shawn.lin@...k-chips.com>
Subject: [PATCH 1/2] Documentation: bindings: add dt documentation for Rockchip PCIe PHY
This patch adds a binding that describes the Rockchip PCIe PHY
found on Rockchip SoCs PCIe interface.
Signed-off-by: Shawn Lin <shawn.lin@...k-chips.com>
---
.../devicetree/bindings/phy/rockchip-pcie-phy.txt | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
new file mode 100644
index 0000000..ba8c406
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
@@ -0,0 +1,22 @@
+Rockchip PCIE PHY
+-----------------------
+
+Required properties:
+ - compatible: rockchip,rk3399-pcie-phy
+ - #phy-cells: must be 0
+
+Example:
+
+grf: syscon@...70000 {
+ compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ...
+
+ pcie_phy: phy@...0 {
+ compatible = "rockchip,rk3399-pcie-phy";
+ #phy-cells = <0>;
+ };
+};
+
--
2.3.7
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