| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <tip-0cc6d9688e55d17c884e6bfdb0074b77d2945b1b@git.kernel.org> Date: Wed, 8 Jun 2016 02:56:02 -0700 From: tip-bot for Dave Hansen <tipbot@...or.com> To: linux-tip-commits@...r.kernel.org Cc: dave@...1.net, lenb@...nel.org, dvhart@...radead.org, eranian@...gle.com, vishwanath.somayaji@...el.com, tony.luck@...el.com, rui.zhang@...el.com, edubezval@...il.com, mchehab@....samsung.com, dougthompson@...ssion.com, ulf.hansson@...aro.org, jacob.jun.pan@...ux.intel.com, mingo@...nel.org, tglx@...utronix.de, rajneesh.bhardwaj@...el.com, adrian.hunter@...el.com, kan.liang@...el.com, dvlasenk@...hat.com, souvik.k.chakravarty@...el.com, viresh.kumar@...aro.org, brgerst@...il.com, rafael.j.wysocki@...el.com, peterz@...radead.org, hpa@...or.com, torvalds@...ux-foundation.org, dave.hansen@...ux.intel.com, luto@...nel.org, luto@...capital.net, bp@...en8.de, linux-kernel@...r.kernel.org, srinivas.pandruvada@...ux.intel.com Subject: [tip:x86/urgent] x86/cpu/intel: Introduce macros for Intel family numbers Commit-ID: 0cc6d9688e55d17c884e6bfdb0074b77d2945b1b Gitweb: http://git.kernel.org/tip/0cc6d9688e55d17c884e6bfdb0074b77d2945b1b Author: Dave Hansen <dave@...1.net> AuthorDate: Thu, 2 Jun 2016 17:19:27 -0700 Committer: Ingo Molnar <mingo@...nel.org> CommitDate: Wed, 8 Jun 2016 11:48:39 +0200 x86/cpu/intel: Introduce macros for Intel family numbers Problem: We have a boatload of open-coded family-6 model numbers. Half of them have these model numbers in hex and the other half in decimal. This makes grepping for them tons of fun, if you were to try. Solution: Consolidate all the magic numbers. Put all the definitions in one header. The names here are closely derived from the comments describing the models from arch/x86/events/intel/core.c. We could easily make them shorter by doing things like s/SANDYBRIDGE/SNB/, but they seemed fine even with the longer versions to me. Do not take any of these names too literally, like "DESKTOP" or "MOBILE". These are all colloquial names and not precise descriptions of everywhere a given model will show up. Signed-off-by: Dave Hansen <dave.hansen@...ux.intel.com> Cc: Adrian Hunter <adrian.hunter@...el.com> Cc: Andy Lutomirski <luto@...capital.net> Cc: Andy Lutomirski <luto@...nel.org> Cc: Borislav Petkov <bp@...en8.de> Cc: Brian Gerst <brgerst@...il.com> Cc: Darren Hart <dvhart@...radead.org> Cc: Dave Hansen <dave@...1.net> Cc: Denys Vlasenko <dvlasenk@...hat.com> Cc: Doug Thompson <dougthompson@...ssion.com> Cc: Eduardo Valentin <edubezval@...il.com> Cc: H. Peter Anvin <hpa@...or.com> Cc: Jacob Pan <jacob.jun.pan@...ux.intel.com> Cc: Kan Liang <kan.liang@...el.com> Cc: Len Brown <lenb@...nel.org> Cc: Linus Torvalds <torvalds@...ux-foundation.org> Cc: Mauro Carvalho Chehab <mchehab@....samsung.com> Cc: Peter Zijlstra <peterz@...radead.org> Cc: Rafael J. Wysocki <rafael.j.wysocki@...el.com> Cc: Rajneesh Bhardwaj <rajneesh.bhardwaj@...el.com> Cc: Souvik Kumar Chakravarty <souvik.k.chakravarty@...el.com> Cc: Srinivas Pandruvada <srinivas.pandruvada@...ux.intel.com> Cc: Stephane Eranian <eranian@...gle.com> Cc: Thomas Gleixner <tglx@...utronix.de> Cc: Tony Luck <tony.luck@...el.com> Cc: Ulf Hansson <ulf.hansson@...aro.org> Cc: Viresh Kumar <viresh.kumar@...aro.org> Cc: Vishwanath Somayaji <vishwanath.somayaji@...el.com> Cc: Zhang Rui <rui.zhang@...el.com> Cc: jacob.jun.pan@...el.com Cc: linux-acpi@...r.kernel.org Cc: linux-edac@...r.kernel.org Cc: linux-mmc@...r.kernel.org Cc: linux-pm@...r.kernel.org Cc: platform-driver-x86@...r.kernel.org Link: http://lkml.kernel.org/r/20160603001927.F2A7D828@viggo.jf.intel.com Signed-off-by: Ingo Molnar <mingo@...nel.org> --- arch/x86/include/asm/intel-family.h | 62 +++++++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h new file mode 100644 index 0000000..7b142ff --- /dev/null +++ b/arch/x86/include/asm/intel-family.h @@ -0,0 +1,62 @@ +#ifndef _ASM_X86_INTEL_FAMILY_H +#define _ASM_X86_INTEL_FAMILY_H + +/* + * "Big Core" Processors (Branded as Core, Xeon, etc...) + * + * The "_X" parts are generally the EP and EX Xeons, or the + * "Extreme" ones, like Broadwell-E. + */ + +#define INTEL_FAM6_CORE_YONAH 0x0E +#define INTEL_FAM6_CORE2_MEROM 0x0F +#define INTEL_FAM6_CORE2_MEROM_L 0x16 +#define INTEL_FAM6_CORE2_PENRYN 0x17 +#define INTEL_FAM6_CORE2_DUNNINGTON 0x1D + +#define INTEL_FAM6_NEHALEM 0x1E +#define INTEL_FAM6_NEHALEM_EP 0x1A +#define INTEL_FAM6_NEHALEM_EX 0x2E +#define INTEL_FAM6_WESTMERE 0x25 +#define INTEL_FAM6_WESTMERE_EP 0x2C +#define INTEL_FAM6_WESTMERE_EX 0x2F + +#define INTEL_FAM6_SANDYBRIDGE 0x2A +#define INTEL_FAM6_SANDYBRIDGE_X 0x2D +#define INTEL_FAM6_IVYBRIDGE 0x3A +#define INTEL_FAM6_IVYBRIDGE_X 0x3E + +#define INTEL_FAM6_HASWELL_CORE 0x3C +#define INTEL_FAM6_HASWELL_X 0x3F +#define INTEL_FAM6_HASWELL_ULT 0x45 +#define INTEL_FAM6_HASWELL_GT3E 0x46 + +#define INTEL_FAM6_BROADWELL_CORE 0x3D +#define INTEL_FAM6_BROADWELL_XEON_D 0x56 +#define INTEL_FAM6_BROADWELL_GT3E 0x47 +#define INTEL_FAM6_BROADWELL_X 0x4F + +#define INTEL_FAM6_SKYLAKE_MOBILE 0x4E +#define INTEL_FAM6_SKYLAKE_DESKTOP 0x5E +#define INTEL_FAM6_SKYLAKE_X 0x55 +#define INTEL_FAM6_KABYLAKE_MOBILE 0x8E +#define INTEL_FAM6_KABYLAKE_DESKTOP 0x9E + +/* "Small Core" Processors (Atom) */ + +#define INTEL_FAM6_ATOM_PINEVIEW 0x1C +#define INTEL_FAM6_ATOM_LINCROFT 0x26 +#define INTEL_FAM6_ATOM_PENWELL 0x27 +#define INTEL_FAM6_ATOM_CLOVERVIEW 0x35 +#define INTEL_FAM6_ATOM_CEDARVIEW 0x36 +#define INTEL_FAM6_ATOM_SILVERMONT1 0x37 +#define INTEL_FAM6_ATOM_SILVERMONT2 0x4D /* Avaton/Rangely */ +#define INTEL_FAM6_ATOM_AIRMONT 0x4C +#define INTEL_FAM6_ATOM_GOLDMONT 0x5C +#define INTEL_FAM6_ATOM_DENVERTON 0x5F /* Goldmont Microserver */ + +/* Xeon Phi */ + +#define INTEL_FAM6_XEON_PHI_KNL 0x57 /* Knights Landing */ + +#endif /* _ASM_X86_INTEL_FAMILY_H */
Powered by blists - more mailing lists