linux-kernel - [tip:perf/core] perf/x86/msr: Add missing Intel models

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Message-ID: <tip-5134596caee9e834d2486edc45efad4c9e6effc3@git.kernel.org>
Date:	Wed, 8 Jun 2016 04:02:21 -0700
From:	tip-bot for Dave Hansen <tipbot@...or.com>
To:	linux-tip-commits@...r.kernel.org
Cc:	luto@...capital.net, alexander.shishkin@...ux.intel.com,
	dave.hansen@...ux.intel.com, eranian@...gle.com,
	dvlasenk@...hat.com, peterz@...radead.org,
	torvalds@...ux-foundation.org, bp@...en8.de, acme@...hat.com,
	brgerst@...il.com, hpa@...or.com, tglx@...utronix.de,
	vincent.weaver@...ne.edu, dave@...1.net, jolsa@...hat.com,
	mingo@...nel.org, linux-kernel@...r.kernel.org
Subject: [tip:perf/core] perf/x86/msr: Add missing Intel models

Commit-ID:  5134596caee9e834d2486edc45efad4c9e6effc3
Gitweb:     http://git.kernel.org/tip/5134596caee9e834d2486edc45efad4c9e6effc3
Author:     Dave Hansen <dave.hansen@...ux.intel.com>
AuthorDate: Thu, 2 Jun 2016 17:19:35 -0700
Committer:  Ingo Molnar <mingo@...nel.org>
CommitDate: Wed, 8 Jun 2016 12:05:59 +0200

perf/x86/msr: Add missing Intel models

This patch presumes that Kabylake and Skylake Server will be the
same as the existing Skylake parts and adds them to the MSR
events code.

Also add handling for "WESTMERE2".

Signed-off-by: Dave Hansen <dave.hansen@...ux.intel.com>
Cc: Alexander Shishkin <alexander.shishkin@...ux.intel.com>
Cc: Andy Lutomirski <luto@...capital.net>
Cc: Arnaldo Carvalho de Melo <acme@...hat.com>
Cc: Borislav Petkov <bp@...en8.de>
Cc: Brian Gerst <brgerst@...il.com>
Cc: Dave Hansen <dave@...1.net>
Cc: Denys Vlasenko <dvlasenk@...hat.com>
Cc: H. Peter Anvin <hpa@...or.com>
Cc: Jiri Olsa <jolsa@...hat.com>
Cc: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Stephane Eranian <eranian@...gle.com>
Cc: Thomas Gleixner <tglx@...utronix.de>
Cc: Vince Weaver <vincent.weaver@...ne.edu>
Cc: jacob.jun.pan@...el.com
Link: http://lkml.kernel.org/r/20160603001935.FE6B3847@viggo.jf.intel.com
Signed-off-by: Ingo Molnar <mingo@...nel.org>
---
 arch/x86/events/msr.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
index 83cf13e..50b3a05 100644
--- a/arch/x86/events/msr.c
+++ b/arch/x86/events/msr.c
@@ -40,6 +40,7 @@ static bool test_intel(int idx)
 	case INTEL_FAM6_NEHALEM_EX:
 
 	case INTEL_FAM6_WESTMERE:
+	case INTEL_FAM6_WESTMERE2:
 	case INTEL_FAM6_WESTMERE_EP:
 	case INTEL_FAM6_WESTMERE_EX:
 
@@ -68,6 +69,9 @@ static bool test_intel(int idx)
 
 	case INTEL_FAM6_SKYLAKE_MOBILE:
 	case INTEL_FAM6_SKYLAKE_DESKTOP:
+	case INTEL_FAM6_SKYLAKE_X:
+	case INTEL_FAM6_KABYLAKE_MOBILE:
+	case INTEL_FAM6_KABYLAKE_DESKTOP:
 		if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)
 			return true;
 		break;