linux-kernel - [PATCH 7/8] tty: serial: fsl-lpuart: Update suspend/resume for DMA mode

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Message-ID: <20160609151039.20817-8-bhuvanchandra.dv@toradex.com>
Date:	Thu, 9 Jun 2016 20:40:38 +0530
From:	Bhuvanchandra DV <bhuvanchandra.dv@...adex.com>
To:	<gregkh@...uxfoundation.org>
CC:	<stefan@...er.ch>, <shawnguo@...nel.org>, <kernel@...gutronix.de>,
	<mturquette@...libre.com>, <sboyd@...eaurora.org>,
	<jslaby@...e.com>, <linux-arm-kernel@...ts.infradead.org>,
	<linux-clk@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
	<linux-serial@...r.kernel.org>,
	"Bhuvanchandra DV" <bhuvanchandra.dv@...adex.com>
Subject: [PATCH 7/8] tty: serial: fsl-lpuart: Update suspend/resume for DMA mode

When DMA mode is enabled one need to make sure the DMA channels are
idle before entering suspend mode especially when UART ports which
are set as wakeup source and console port with no_console_suspend
is set. This patch takes care of gracefully releasing DMA channels
for the above two cases and start the DMA at resume.

Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@...adex.com>
---
 drivers/tty/serial/fsl_lpuart.c | 44 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c
index 27687d5..134090a 100644
--- a/drivers/tty/serial/fsl_lpuart.c
+++ b/drivers/tty/serial/fsl_lpuart.c
@@ -1943,6 +1943,30 @@ static int lpuart_suspend(struct device *dev)
 	}
 
 	uart_suspend_port(&lpuart_reg, &sport->port);
+
+	if (sport->lpuart_dma_rx_use) {
+		/*
+		 * EDMA driver during suspend will forcefully release any
+		 * non-idle DMA channels. If port wakeup is enabled or if port
+		 * is console port or 'no_console_suspend' is set the Rx DMA
+		 * cannot resume as as expected, hence gracefully release the
+		 * Rx DMA path before suspend and start Rx DMA path on resume.
+		 */
+		if (sport->port.irq_wake) {
+			del_timer_sync(&sport->lpuart_timer);
+			lpuart_dma_rx_free(&sport->port);
+		}
+
+		/* Disable Rx DMA to use UART port as wakeup source */
+		writeb(readb(sport->port.membase + UARTCR5) & ~UARTCR5_RDMAS,
+					sport->port.membase + UARTCR5);
+	}
+
+	if (sport->lpuart_dma_tx_use) {
+		sport->dma_tx_in_progress = false;
+		dmaengine_terminate_all(sport->dma_tx_chan);
+	}
+
 	if (sport->port.suspended && !sport->port.irq_wake)
 		clk_disable_unprepare(sport->clk);
 
@@ -1970,6 +1994,26 @@ static int lpuart_resume(struct device *dev)
 		writeb(temp, sport->port.membase + UARTCR2);
 	}
 
+	if (sport->lpuart_dma_rx_use) {
+		if (sport->port.irq_wake) {
+			if (!lpuart_start_rx_dma(sport)) {
+				sport->lpuart_dma_rx_use = true;
+				rx_dma_timer_init(sport);
+			} else {
+				sport->lpuart_dma_rx_use = false;
+			}
+		}
+	}
+
+	if (sport->dma_tx_chan && !lpuart_dma_tx_request(&sport->port)) {
+			init_waitqueue_head(&sport->dma_wait);
+			sport->lpuart_dma_tx_use = true;
+			writeb(readb(sport->port.membase + UARTCR5) |
+				UARTCR5_TDMAS, sport->port.membase + UARTCR5);
+	} else {
+		sport->lpuart_dma_tx_use = false;
+	}
+
 	uart_resume_port(&lpuart_reg, &sport->port);
 
 	return 0;
-- 
2.8.3