linux-kernel - Re: [PATCH v2 2/2] PCI: Rockchip: Add Rockchip PCIe controller support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Date:	Fri, 10 Jun 2016 08:37:51 +0100
From:	Marc Zyngier <marc.zyngier@....com>
To:	Doug Anderson <dianders@...omium.org>
Cc:	Shawn Lin <shawn.lin@...k-chips.com>,
	Bjorn Helgaas <bhelgaas@...gle.com>, linux-pci@...r.kernel.org,
	Arnd Bergmann <arnd@...db.de>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"open list:ARM/Rockchip SoC..." <linux-rockchip@...ts.infradead.org>,
	Heiko Stuebner <heiko@...ech.de>,
	Wenrui Li <wenrui.li@...k-chips.com>,
	Rob Herring <robh+dt@...nel.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>
Subject: Re: [PATCH v2 2/2] PCI: Rockchip: Add Rockchip PCIe controller
 support

On Thu, 9 Jun 2016 21:00:08 -0700
Doug Anderson <dianders@...omium.org> wrote:

Hi Doug,

> Shawn,
> 
> On Wed, Jun 8, 2016 at 1:05 AM, Shawn Lin <shawn.lin@...k-chips.com> wrote:
> > This patch adds Rockchip PCIe controller support found
> > on RK3399 Soc platform.
> >
> > Signed-off-by: Shawn Lin <shawn.lin@...k-chips.com>
> >
> > ---
> >
> > Changes in v2:
> > - remove phy related stuff and call phy API
> > - add new head file and define lots of macro to make
> >   the code more readable
> > - remove lots msi related code suggested by Marc
> > - add IO window address translation
> > - init_port and parse_dt reconstruction suggested by Bharat
> > - improve wr_own_conf suggested by Arnd
> > - make pcie as an interrupt controller and fix wrong int handler
> >   suggested by Marc
> > - remove PCI_PROBE_ONLY suggested by Lorenzo
> >
> >  drivers/pci/host/Kconfig         |   11 +
> >  drivers/pci/host/Makefile        |    1 +
> >  drivers/pci/host/pcie-rockchip.c | 1049 ++++++++++++++++++++++++++++++++++++++
> >  drivers/pci/host/pcie-rockchip.h |  209 ++++++++
> >  4 files changed, 1270 insertions(+)
> 
> A few drive-by comments for things I ran into trying to get this
> working.  I'm no PCI expert.
> 
> 
> > +config PCIE_ROCKCHIP
> > +       bool "Rockchip PCIe controller"
> > +       depends on ARM64 && ARCH_ROCKCHIP
> > +       depends on OF
> > +       select MFD_SYSCON
> > +       select PCI_MSI_IRQ_DOMAIN if PCI_MSI
> 
> Probably because I don't know what I'm doing, but when I had PCI_MSI
> configured I had trouble getting interrupts.  Figured I'd mention it
> even though it's probably user error.

Could you please elaborate on this? Do you see MSIs being
allocated but not delivered? Or something else?

The reason I'm asking is that it is very easy to end-up with MSIs
issues with the GICv3 ITS if there is *anything* between the RC and the
ITS. Typically, you'd have an SMMU that could potentially remap PCIe
Requested IDs to Device IDs. Short of describing transformations in the
msi-map property, you could end-up with no MSI being delivered.

Please let me know if I can help.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny.