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Message-ID: <20160611081403.GD92337@worksta>
Date: Sat, 11 Jun 2016 01:14:03 -0700
From: Bin Gao <bin.gao@...ux.intel.com>
To: Zhang Rui <rui.zhang@...el.com>, Lee Jones <lee.jones@...aro.org>,
Eduardo Valentin <edubezval@...il.com>,
linux-kernel@...r.kernel.org
Cc: ysiyer <yegnesh.s.iyer@...el.com>,
Ajay Thomas <ajay.thomas.david.rajamanickam@...el.com>,
Bin Gao <bin.gao@...el.com>
Subject: [PATCH 3/3] mfd/intel_soc_pmic_bxtwc: add Intel BXT WhiskeyCove PMIC
ADC thermal channel-zone mapping
This changes adds the mapping of Intel BXT WhiskeyCove PMIC ADC channel
to thermal zone. This mapping is used in the pmic thermal driver to
notify the thermal zone with the pmic adc channel alert interrupts.
Signed-off-by: Yegnesh Iyer <yegnesh.s.iyer@...el.com>
Signed-off-by: Bin Gao <bin.gao@...el.com>
---
drivers/mfd/intel_soc_pmic_bxtwc.c | 109 +++++++++++++++++++++++++++++++++++++
1 file changed, 109 insertions(+)
diff --git a/drivers/mfd/intel_soc_pmic_bxtwc.c b/drivers/mfd/intel_soc_pmic_bxtwc.c
index b942876..ec50788 100644
--- a/drivers/mfd/intel_soc_pmic_bxtwc.c
+++ b/drivers/mfd/intel_soc_pmic_bxtwc.c
@@ -58,6 +58,10 @@
#define BXTWC_MGPIO1IRQ 0x4E1A
#define BXTWC_MCRITIRQ 0x4E1B
+#define BXTWC_STHRM0IRQ 0x4F19
+#define BXTWC_STHRM1IRQ 0x4F1A
+#define BXTWC_STHRM2IRQ 0x4F1B
+
/* Whiskey Cove PMIC share same ACPI ID between different platforms */
#define BROXTON_PMIC_WC_HRV 4
@@ -116,6 +120,109 @@ static const struct regmap_irq bxtwc_regmap_irqs_level2[] = {
REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 9, 0x03),
};
+static struct trip_config_map str0_trip_config[] = {
+ {
+ .irq_reg = BXTWC_THRM0IRQ,
+ .irq_mask = 0x01,
+ .irq_en = BXTWC_MTHRM0IRQ,
+ .irq_en_mask = 0x01,
+ .evt_stat = BXTWC_STHRM0IRQ,
+ .evt_mask = 0x01,
+ .trip_num = 0
+ },
+ {
+ .irq_reg = BXTWC_THRM0IRQ,
+ .irq_mask = 0x10,
+ .irq_en = BXTWC_MTHRM0IRQ,
+ .irq_en_mask = 0x10,
+ .evt_stat = BXTWC_STHRM0IRQ,
+ .evt_mask = 0x10,
+ .trip_num = 1
+ }
+};
+
+static struct trip_config_map str1_trip_config[] = {
+ {
+ .irq_reg = BXTWC_THRM0IRQ,
+ .irq_mask = 0x02,
+ .irq_en = BXTWC_MTHRM0IRQ,
+ .irq_en_mask = 0x02,
+ .evt_stat = BXTWC_STHRM0IRQ,
+ .evt_mask = 0x02,
+ .trip_num = 0
+ },
+ {
+ .irq_reg = BXTWC_THRM0IRQ,
+ .irq_mask = 0x20,
+ .irq_en = BXTWC_MTHRM0IRQ,
+ .irq_en_mask = 0x20,
+ .evt_stat = BXTWC_STHRM0IRQ,
+ .evt_mask = 0x20,
+ .trip_num = 1
+ },
+};
+
+static struct trip_config_map str2_trip_config[] = {
+ {
+ .irq_reg = BXTWC_THRM0IRQ,
+ .irq_mask = 0x04,
+ .irq_en = BXTWC_MTHRM0IRQ,
+ .irq_en_mask = 0x04,
+ .evt_stat = BXTWC_STHRM0IRQ,
+ .evt_mask = 0x04,
+ .trip_num = 0
+ },
+ {
+ .irq_reg = BXTWC_THRM0IRQ,
+ .irq_mask = 0x40,
+ .irq_en = BXTWC_MTHRM0IRQ,
+ .irq_en_mask = 0x40,
+ .evt_stat = BXTWC_STHRM0IRQ,
+ .evt_mask = 0x40,
+ .trip_num = 1
+ },
+};
+
+static struct trip_config_map str3_trip_config[] = {
+ {
+ .irq_reg = BXTWC_THRM2IRQ,
+ .irq_mask = 0x10,
+ .irq_en = BXTWC_MTHRM2IRQ,
+ .irq_en_mask = 0x10,
+ .evt_stat = BXTWC_STHRM2IRQ,
+ .evt_mask = 0x10,
+ .trip_num = 0
+ },
+};
+
+static struct thermal_irq_map bxtwc_thermal_irq_map[] = {
+ {
+ .handle = "STR0",
+ .trip_config = str0_trip_config,
+ .num_trips = ARRAY_SIZE(str0_trip_config),
+ },
+ {
+ .handle = "STR1",
+ .trip_config = str1_trip_config,
+ .num_trips = ARRAY_SIZE(str1_trip_config),
+ },
+ {
+ .handle = "STR2",
+ .trip_config = str2_trip_config,
+ .num_trips = ARRAY_SIZE(str2_trip_config),
+ },
+ {
+ .handle = "STR3",
+ .trip_config = str3_trip_config,
+ .num_trips = ARRAY_SIZE(str3_trip_config),
+ },
+};
+
+static struct pmic_thermal_data bxtwc_thermal_data = {
+ .maps = bxtwc_thermal_irq_map,
+ .num_maps = ARRAY_SIZE(bxtwc_thermal_irq_map),
+};
+
static struct regmap_irq_chip bxtwc_regmap_irq_chip = {
.name = "bxtwc_irq_chip",
.status_base = BXTWC_IRQLVL1,
@@ -168,6 +275,8 @@ static struct mfd_cell bxt_wc_dev[] = {
.name = "bxt_wcove_thermal",
.num_resources = ARRAY_SIZE(thermal_resources),
.resources = thermal_resources,
+ .platform_data = &bxtwc_thermal_data,
+ .pdata_size = sizeof(bxtwc_thermal_data),
},
{
.name = "bxt_wcove_ext_charger",
--
1.9.1
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