lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:	Sun, 12 Jun 2016 18:46:51 +0800
From:	Yakir Yang <ykk@...k-chips.com>
To:	Xing Zheng <zhengxing@...k-chips.com>, heiko@...ech.de
Cc:	dianders@...omium.org, elaine.zhang@...k-chips.com,
	huangtao@...k-chips.com, briannorris@...omium.org,
	Michael Turquette <mturquette@...libre.com>,
	Stephen Boyd <sboyd@...eaurora.org>, linux-clk@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org,
	linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] clk: rockchip: add flag CLK_SET_RATE_PARENT for
 dclk_vop0_div on RK3399

Xing,

On 06/12/2016 05:48 PM, Xing Zheng wrote:
> The functions and features VOP0 more complete than VOP1's, we need to
> use it dclk_vop0_div operate VPLLI, and let VOP0 as the default primary
> screen.
>
> Signed-off-by: Xing Zheng <zhengxing@...k-chips.com>

Tested on RK3399 Kevin board, after apply this patch, my eDP panel light 
up normally. So

Tested-by: Yakir Yang <ykk@...k-chips.com>

BR,
- Yakir

> ---
>
>   drivers/clk/rockchip/clk-rk3399.c |    2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
> index 7ecb12c3..6affa75 100644
> --- a/drivers/clk/rockchip/clk-rk3399.c
> +++ b/drivers/clk/rockchip/clk-rk3399.c
> @@ -1157,7 +1157,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
>   	GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IGNORE_UNUSED,
>   			RK3399_CLKGATE_CON(28), 0, GFLAGS),
>   
> -	COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, 0,
> +	COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, CLK_SET_RATE_PARENT,
>   			RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS,
>   			RK3399_CLKGATE_CON(10), 12, GFLAGS),
>   


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ