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Message-ID: <20160613155907.GB1740@lahna.fi.intel.com>
Date:	Mon, 13 Jun 2016 18:59:07 +0300
From:	Mika Westerberg <mika.westerberg@...ux.intel.com>
To:	Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
Cc:	Tan Jui Nee <jui.nee.tan@...el.com>,
	heikki.krogerus@...ux.intel.com, tglx@...utronix.de,
	mingo@...hat.com, hpa@...or.com, x86@...nel.org,
	ptyser@...-inc.com, lee.jones@...aro.org,
	linux-gpio@...r.kernel.org, linux-kernel@...r.kernel.org,
	jonathan.yong@...el.com, ong.hock.yu@...el.com,
	weifeng.voon@...el.com, wan.ahmad.zainie.wan.mohamad@...el.com
Subject: Re: [PATCH v3 2/3] x86/platform/p2sb: New Primary to Sideband bridge
 support driver for Intel SOC's

On Mon, Jun 13, 2016 at 06:19:12PM +0300, Andy Shevchenko wrote:
> On Mon, 2016-06-13 at 17:25 +0300, Mika Westerberg wrote:
> > On Mon, Jun 13, 2016 at 04:54:31PM +0300, Andy Shevchenko wrote:
> > > Would work to me, though still the same question: is it possible to
> > > avoid building it on even most of Intel platforms, since there, I
> > > assume, will be not many users of the module?
> > 
> > Well, even if you make it configurable via Kconfig, I guess distros
> > will
> > have to enable it in order to support as wide range of CPUs as
> > possible
> > in a single binary.
> 
> Good point.
> 
> Then perhaps the following we can do:
>  - add a static boolean flag
>  - add __init function where we check either PCI root bridge ID or CPU
> ID (I don't know which one is better, I suppose second one, though it
> will require an update of arch/x86/include/asm/intel-family.h)
>  - add a check into the function.
> 
> What do you think?

Maybe, or make it modular and use MODULE_DEVICE_TABLE(x86cpu, ...) to
match the corresponding CPUs.

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