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Message-Id: <1465985877-18271-7-git-send-email-juri.lelli@arm.com>
Date: Wed, 15 Jun 2016 11:17:55 +0100
From: Juri Lelli <juri.lelli@....com>
To: linux-kernel@...r.kernel.org
Cc: linux-pm@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
devicetree@...r.kernel.org, peterz@...radead.org,
vincent.guittot@...aro.org, robh+dt@...nel.org,
mark.rutland@....com, linux@....linux.org.uk, sudeep.holla@....com,
lorenzo.pieralisi@....com, catalin.marinas@....com,
will.deacon@....com, morten.rasmussen@....com,
dietmar.eggemann@....com, juri.lelli@....com, broonie@...nel.org,
sgurrappadi@...dia.com, Pawel Moll <pawel.moll@....com>,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
Kumar Gala <galak@...eaurora.org>,
Liviu Dudau <Liviu.Dudau@....com>,
Arnd Bergmann <arnd@...db.de>, Jon Medhurst <tixy@...aro.org>,
Olof Johansson <olof@...om.net>,
Robin Murphy <robin.murphy@....com>
Subject: [PATCH v5 6/8] arm64, dts: add Juno r2 cpu capacity-dmips-mhz information
Add Juno r2 cpu capacity-dmips-mhz bindings information.
Cc: Rob Herring <robh+dt@...nel.org>
Cc: Pawel Moll <pawel.moll@....com>
Cc: Mark Rutland <mark.rutland@....com>
Cc: Ian Campbell <ijc+devicetree@...lion.org.uk>
Cc: Kumar Gala <galak@...eaurora.org>
Cc: Catalin Marinas <catalin.marinas@....com>
Cc: Will Deacon <will.deacon@....com>
Cc: Liviu Dudau <Liviu.Dudau@....com>
Cc: Sudeep Holla <sudeep.holla@....com>
Cc: Arnd Bergmann <arnd@...db.de>
Cc: Jon Medhurst <tixy@...aro.org>
Cc: Olof Johansson <olof@...om.net>
Cc: Robin Murphy <robin.murphy@....com>
Cc: devicetree@...r.kernel.org
Signed-off-by: Juri Lelli <juri.lelli@....com>
---
Changes from v4:
- new patch since Juno r2 dt has been merged
---
arch/arm64/boot/dts/arm/juno-r2.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts
index 88ecd61..823b614b 100644
--- a/arch/arm64/boot/dts/arm/juno-r2.dts
+++ b/arch/arm64/boot/dts/arm/juno-r2.dts
@@ -90,6 +90,7 @@
next-level-cache = <&A72_L2>;
clocks = <&scpi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ capacity-dmips-mhz = <1024>;
};
A72_1: cpu@1 {
@@ -100,6 +101,7 @@
next-level-cache = <&A72_L2>;
clocks = <&scpi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ capacity-dmips-mhz = <1024>;
};
A53_0: cpu@100 {
@@ -110,6 +112,7 @@
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ capacity-dmips-mhz = <485>;
};
A53_1: cpu@101 {
@@ -120,6 +123,7 @@
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ capacity-dmips-mhz = <485>;
};
A53_2: cpu@102 {
@@ -130,6 +134,7 @@
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ capacity-dmips-mhz = <485>;
};
A53_3: cpu@103 {
@@ -140,6 +145,7 @@
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ capacity-dmips-mhz = <485>;
};
A72_L2: l2-cache0 {
--
2.7.0
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