| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <5762A024.9040408@163.com>
Date: Thu, 16 Jun 2016 20:48:36 +0800
From: Kever Yang <ellisys@....com>
To: Chris Zhong <zyw@...k-chips.com>, dianders@...omium.org,
tfiga@...omium.org, heiko@...ech.de, yzq@...k-chips.com,
groeck@...omium.org
CC: Kever Yang <kever.yang@...k-chips.com>,
linux-kernel@...r.kernel.org, linux-rockchip@...ts.infradead.org,
Kishon Vijay Abraham I <kishon@...com>,
linux-arm-kernel@...ts.infradead.org
Subject: Re: [v2 PATCH 2/4] phy: Add USB Type-C PHY driver for rk3399
Hi Chris,
On 06/13/2016 05:39 PM, Chris Zhong wrote:
> Add a PHY provider driver for the rk3399 SoC Type-c PHY. The USB
> Type-C PHY is designed to support the USB3 and DP applications. The
> PHY basically has two main components: USB3 and DisplyPort. USB3
> operates in SuperSpeed mode and the DP can operate at RBR, HBR and
> HBR2 data rates.
>
> Signed-off-by: Chris Zhong <zyw@...k-chips.com>
> Signed-off-by: Kever Yang <kever.yang@...k-chips.com>
>
> ---
>
> Changes in v2:
> - select RESET_CONTROLLER
> - alphabetic order
> - modify some spelling mistakes
> - make mode cleaner
> - use bool for enable/disable
> - check all of the return value
> - return a better err number
> - use more readx_poll_timeout()
> - clk_disable_unprepare(tcphy->clk_ref);
> - remove unuse functions, rockchip_typec_phy_power_on/off
> - remove unnecessary typecast from void *
> - use dts node to distinguish between phys.
>
> Changes in v1:
> - update the licence note
> - init core clock to 50MHz
> - use extcon API
> - remove unused global
> - add some comments for magic num
> - change usleep_range(1000, 2000) tousleep_range(1000, 1050)
> - remove __func__ from dev_err
> - return err number when get clk failed
> - remove ADDR_ADJ define
> - use devm_clk_get(&pdev->dev, "tcpdcore")
>
> drivers/phy/Kconfig | 8 +
> drivers/phy/Makefile | 1 +
> drivers/phy/phy-rockchip-typec.c | 952 +++++++++++++++++++++++++++++++++
> include/linux/phy/phy-rockchip-typec.h | 20 +
> 4 files changed, 981 insertions(+)
> create mode 100644 drivers/phy/phy-rockchip-typec.c
> create mode 100644 include/linux/phy/phy-rockchip-typec.h
>
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 26566db..ec87b3a 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -351,6 +351,14 @@ config PHY_ROCKCHIP_DP
> help
> Enable this to support the Rockchip Display Port PHY.
>
> +config PHY_ROCKCHIP_TYPEC
> + tristate "Rockchip TYPEC PHY Driver"
> + depends on ARCH_ROCKCHIP && OF
> + select GENERIC_PHY
> + select RESET_CONTROLLER
> + help
> + Enable this to support the Rockchip USB TYPEC PHY.
> +
> config PHY_ST_SPEAR1310_MIPHY
> tristate "ST SPEAR1310-MIPHY driver"
> select GENERIC_PHY
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index 24596a9..91fa413 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -39,6 +39,7 @@ obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
> obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
> obj-$(CONFIG_PHY_ROCKCHIP_EMMC) += phy-rockchip-emmc.o
> obj-$(CONFIG_PHY_ROCKCHIP_DP) += phy-rockchip-dp.o
> +obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o
> obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
> obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o
> obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
> diff --git a/drivers/phy/phy-rockchip-typec.c b/drivers/phy/phy-rockchip-typec.c
> new file mode 100644
> index 0000000..230e074
> --- /dev/null
> +++ b/drivers/phy/phy-rockchip-typec.c
> @@ -0,0 +1,952 @@
> +/*
> + * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
> + * Author: Chris Zhong <zyw@...k-chips.com>
> + * Kever Yang <kever.yang@...k-chips.com>
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/delay.h>
> +#include <linux/extcon.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/mutex.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/reset.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/phy/phy.h>
> +#include <linux/phy/phy-rockchip-typec.h>
> +
> +#define CMN_SSM_BANDGAP (0x21 << 2)
> +#define CMN_SSM_BIAS (0x22 << 2)
> +#define CMN_PLLSM0_PLLEN (0x29 << 2)
> +#define CMN_PLLSM0_PLLPRE (0x2a << 2)
> +#define CMN_PLLSM0_PLLVREF (0x2b << 2)
> +#define CMN_PLLSM0_PLLLOCK (0x2c << 2)
> +#define CMN_PLLSM1_PLLEN (0x31 << 2)
> +#define CMN_PLLSM1_PLLPRE (0x32 << 2)
> +#define CMN_PLLSM1_PLLVREF (0x33 << 2)
> +#define CMN_PLLSM1_PLLLOCK (0x34 << 2)
> +#define CMN_PLLSM1_USER_DEF_CTRL (0x37 << 2)
> +#define CMN_ICAL_OVRD (0xc1 << 2)
> +#define CMN_PLL0_VCOCAL_OVRD (0x83 << 2)
> +#define CMN_PLL0_VCOCAL_INIT (0x84 << 2)
> +#define CMN_PLL0_VCOCAL_ITER (0x85 << 2)
> +#define CMN_PLL0_LOCK_REFCNT_START (0x90 << 2)
> +#define CMN_PLL0_LOCK_PLLCNT_START (0x92 << 2)
> +#define CMN_PLL0_LOCK_PLLCNT_THR (0x93 << 2)
> +#define CMN_PLL0_INTDIV (0x94 << 2)
> +#define CMN_PLL0_FRACDIV (0x95 << 2)
> +#define CMN_PLL0_HIGH_THR (0x96 << 2)
> +#define CMN_PLL0_DSM_DIAG (0x97 << 2)
> +#define CMN_PLL0_SS_CTRL1 (0x98 << 2)
> +#define CMN_PLL0_SS_CTRL2 (0x99 << 2)
> +#define CMN_PLL1_VCOCAL_START (0xa1 << 2)
> +#define CMN_PLL1_VCOCAL_OVRD (0xa3 << 2)
> +#define CMN_PLL1_VCOCAL_INIT (0xa4 << 2)
> +#define CMN_PLL1_VCOCAL_ITER (0xa5 << 2)
> +#define CMN_PLL1_LOCK_REFCNT_START (0xb0 << 2)
> +#define CMN_PLL1_LOCK_PLLCNT_START (0xb2 << 2)
> +#define CMN_PLL1_LOCK_PLLCNT_THR (0xb3 << 2)
> +#define CMN_PLL1_INTDIV (0xb4 << 2)
> +#define CMN_PLL1_FRACDIV (0xb5 << 2)
> +#define CMN_PLL1_HIGH_THR (0xb6 << 2)
> +#define CMN_PLL1_DSM_DIAG (0xb7 << 2)
> +#define CMN_PLL1_SS_CTRL1 (0xb8 << 2)
> +#define CMN_PLL1_SS_CTRL2 (0xb9 << 2)
> +#define CMN_RXCAL_OVRD (0xd1 << 2)
> +#define CMN_TXPUCAL_CTRL (0xe0 << 2)
> +#define CMN_TXPUCAL_OVRD (0xe1 << 2)
> +#define CMN_TXPDCAL_OVRD (0xf1 << 2)
> +#define CMN_DIAG_PLL0_FBH_OVRD (0x1c0 << 2)
> +#define CMN_DIAG_PLL0_FBL_OVRD (0x1c1 << 2)
> +#define CMN_DIAG_PLL0_OVRD (0x1c2 << 2)
> +#define CMN_DIAG_PLL0_V2I_TUNE (0x1c5 << 2)
> +#define CMN_DIAG_PLL0_CP_TUNE (0x1c6 << 2)
> +#define CMN_DIAG_PLL0_LF_PROG (0x1c7 << 2)
> +#define CMN_DIAG_PLL1_FBH_OVRD (0x1d0 << 2)
> +#define CMN_DIAG_PLL1_FBL_OVRD (0x1d1 << 2)
> +#define CMN_DIAG_PLL1_OVRD (0x1d2 << 2)
> +#define CMN_DIAG_PLL1_V2I_TUNE (0x1d5 << 2)
> +#define CMN_DIAG_PLL1_CP_TUNE (0x1d6 << 2)
> +#define CMN_DIAG_PLL1_LF_PROG (0x1d7 << 2)
> +#define CMN_DIAG_PLL1_PTATIS_TUNE1 (0x1d8 << 2)
> +#define CMN_DIAG_PLL1_PTATIS_TUNE2 (0x1d9 << 2)
> +#define CMN_DIAG_PLL1_INCLK_CTRL (0x1da << 2)
> +#define CMN_DIAG_HSCLK_SEL (0x1e0 << 2)
> +
> +#define XCVR_PSM_RCTRL(n) ((0x4001 | (n << 9)) << 2)
> +#define XCVR_PSM_CAL_TMR(n) ((0x4002 | (n << 9)) << 2)
> +#define XCVR_PSM_A0IN_TMR(n) ((0x4003 | (n << 9)) << 2)
> +#define TX_TXCC_CAL_SCLR_MULT(n) ((0x4047 | (n << 9)) << 2)
> +#define TX_TXCC_CPOST_MULT_00(n) ((0x404c | (n << 9)) << 2)
> +#define TX_TXCC_CPOST_MULT_01(n) ((0x404d | (n << 9)) << 2)
> +#define TX_TXCC_CPOST_MULT_10(n) ((0x404e | (n << 9)) << 2)
> +#define TX_TXCC_CPOST_MULT_11(n) ((0x404f | (n << 9)) << 2)
> +#define TX_TXCC_MGNFS_MULT_000(n) ((0x4050 | (n << 9)) << 2)
> +#define TX_TXCC_MGNFS_MULT_001(n) ((0x4051 | (n << 9)) << 2)
> +#define TX_TXCC_MGNFS_MULT_010(n) ((0x4052 | (n << 9)) << 2)
> +#define TX_TXCC_MGNFS_MULT_011(n) ((0x4053 | (n << 9)) << 2)
> +#define TX_TXCC_MGNFS_MULT_100(n) ((0x4054 | (n << 9)) << 2)
> +#define TX_TXCC_MGNFS_MULT_101(n) ((0x4055 | (n << 9)) << 2)
> +#define TX_TXCC_MGNFS_MULT_110(n) ((0x4056 | (n << 9)) << 2)
> +#define TX_TXCC_MGNFS_MULT_111(n) ((0x4057 | (n << 9)) << 2)
> +#define XCVR_DIAG_PLLDRC_CTRL(n) ((0x40e0 | (n << 9)) << 2)
> +#define XCVR_DIAG_BIDI_CTRL(n) ((0x40e8 | (n << 9)) << 2)
> +#define XCVR_DIAG_LANE_FCM_EN_MGN(n) ((0x40f2 | (n << 9)) << 2)
> +#define TX_PSC_A0(n) ((0x4100 | (n << 9)) << 2)
> +#define TX_PSC_A1(n) ((0x4101 | (n << 9)) << 2)
> +#define TX_PSC_A2(n) ((0x4102 | (n << 9)) << 2)
> +#define TX_PSC_A3(n) ((0x4103 | (n << 9)) << 2)
> +#define TX_RCVDET_CTRL(n) ((0x4120 | (n << 9)) << 2)
> +#define TX_RCVDET_EN_TMR(n) ((0x4122 | (n << 9)) << 2)
> +#define TX_RCVDET_ST_TMR(n) ((0x4123 | (n << 9)) << 2)
> +#define TX_DIAG_TX_DRV(n) ((0x41e1 | (n << 9)) << 2)
> +#define TX_DIAG_BGREF_PREDRV_DELAY (0x41e7 << 2)
> +#define TX_ANA_CTRL_REG_1 (0x5020 << 2)
> +#define TX_ANA_CTRL_REG_2 (0x5021 << 2)
> +#define TXDA_COEFF_CALC_CTRL (0x5022 << 2)
> +#define TX_DIG_CTRL_REG_2 (0x5024 << 2)
> +#define TXDA_CYA_AUXDA_CYA (0x5025 << 2)
> +#define TX_ANA_CTRL_REG_3 (0x5026 << 2)
> +#define TX_ANA_CTRL_REG_4 (0x5027 << 2)
> +#define TX_ANA_CTRL_REG_5 (0x5029 << 2)
> +
> +#define RX_PSC_A0(n) ((0x8000 | (n << 9)) << 2)
> +#define RX_PSC_A1(n) ((0x8001 | (n << 9)) << 2)
> +#define RX_PSC_A2(n) ((0x8002 | (n << 9)) << 2)
> +#define RX_PSC_A3(n) ((0x8003 | (n << 9)) << 2)
> +#define RX_PSC_CAL(n) ((0x8006 | (n << 9)) << 2)
> +#define RX_PSC_RDY(n) ((0x8007 | (n << 9)) << 2)
> +#define RX_IQPI_ILL_CAL_OVRD (0x8023 << 2)
> +#define RX_EPI_ILL_CAL_OVRD (0x8033 << 2)
> +#define RX_SDCAL0_OVRD (0x8041 << 2)
> +#define RX_SDCAL1_OVRD (0x8049 << 2)
> +#define RX_SLC_INIT (0x806d << 2)
> +#define RX_SLC_RUN (0x806e << 2)
> +#define RX_CDRLF_CNFG2 (0x8081 << 2)
> +#define RX_SIGDET_HL_FILT_TMR(n) ((0x8090 | (n << 9)) << 2)
> +#define RX_SLC_IOP0_OVRD (0x8101 << 2)
> +#define RX_SLC_IOP1_OVRD (0x8105 << 2)
> +#define RX_SLC_QOP0_OVRD (0x8109 << 2)
> +#define RX_SLC_QOP1_OVRD (0x810d << 2)
> +#define RX_SLC_EOP0_OVRD (0x8111 << 2)
> +#define RX_SLC_EOP1_OVRD (0x8115 << 2)
> +#define RX_SLC_ION0_OVRD (0x8119 << 2)
> +#define RX_SLC_ION1_OVRD (0x811d << 2)
> +#define RX_SLC_QON0_OVRD (0x8121 << 2)
> +#define RX_SLC_QON1_OVRD (0x8125 << 2)
> +#define RX_SLC_EON0_OVRD (0x8129 << 2)
> +#define RX_SLC_EON1_OVRD (0x812d << 2)
> +#define RX_SLC_IEP0_OVRD (0x8131 << 2)
> +#define RX_SLC_IEP1_OVRD (0x8135 << 2)
> +#define RX_SLC_QEP0_OVRD (0x8139 << 2)
> +#define RX_SLC_QEP1_OVRD (0x813d << 2)
> +#define RX_SLC_EEP0_OVRD (0x8141 << 2)
> +#define RX_SLC_EEP1_OVRD (0x8145 << 2)
> +#define RX_SLC_IEN0_OVRD (0x8149 << 2)
> +#define RX_SLC_IEN1_OVRD (0x814d << 2)
> +#define RX_SLC_QEN0_OVRD (0x8151 << 2)
> +#define RX_SLC_QEN1_OVRD (0x8155 << 2)
> +#define RX_SLC_EEN0_OVRD (0x8159 << 2)
> +#define RX_SLC_EEN1_OVRD (0x815d << 2)
> +#define RX_DIAG_SIGDET_TUNE(n) ((0x81dc | (n << 9)) << 2)
> +#define RX_DIAG_SC2C_DELAY (0x81e1 << 2)
> +
> +#define PMA_LANE_CFG (0xc000 << 2)
> +#define PIPE_CMN_CTRL1 (0xc001 << 2)
> +#define PIPE_CMN_CTRL2 (0xc002 << 2)
> +#define PIPE_COM_LOCK_CFG1 (0xc003 << 2)
> +#define PIPE_COM_LOCK_CFG2 (0xc004 << 2)
> +#define PIPE_RCV_DET_INH (0xc005 << 2)
> +#define DP_MODE_CTL (0xc008 << 2)
> +#define DP_CLK_CTL (0xc009 << 2)
> +#define STS (0xc00F << 2)
> +#define PHY_ISO_CMN_CTRL (0xc010 << 2)
> +#define PHY_DP_TX_CTL (0xc408 << 2)
> +#define PMA_CMN_CTRL1 (0xc800 << 2)
> +#define PHY_PMA_ISO_CMN_CTRL (0xc810 << 2)
> +#define PHY_ISOLATION_CTRL (0xc81f << 2)
> +#define PHY_PMA_ISO_XCVR_CTRL(n) ((0xcc11 | (n << 6)) << 2)
> +#define PHY_PMA_ISO_LINK_MODE(n) ((0xcc12 | (n << 6)) << 2)
> +#define PHY_PMA_ISO_PWRST_CTRL(n) ((0xcc13 | (n << 6)) << 2)
> +#define PHY_PMA_ISO_TX_DATA_LO(n) ((0xcc14 | (n << 6)) << 2)
> +#define PHY_PMA_ISO_TX_DATA_HI(n) ((0xcc15 | (n << 6)) << 2)
> +#define PHY_PMA_ISO_RX_DATA_LO(n) ((0xcc16 | (n << 6)) << 2)
> +#define PHY_PMA_ISO_RX_DATA_HI(n) ((0xcc17 | (n << 6)) << 2)
> +#define TX_BIST_CTRL(n) ((0x4140 | (n << 9)) << 2)
> +#define TX_BIST_UDDWR(n) ((0x4141 | (n << 9)) << 2)
> +
> +#define CMN_READY BIT(0)
> +
> +#define DP_PLL_CLOCK_ENABLE BIT(2)
> +#define DP_PLL_ENABLE BIT(0)
> +#define DP_PLL_DATA_RATE_RBR ((2 << 12) | (4 << 8))
> +#define DP_PLL_DATA_RATE_HBR ((2 << 12) | (4 << 8))
> +#define DP_PLL_DATA_RATE_HBR2 ((1 << 12) | (2 << 8))
> +
> +#define GRF_SOC_CON26 0x6268
> +#define UPHY_DP_SEL BIT(3)
> +#define UPHY_DP_SEL_MASK BIT(19)
> +#define DPTX_HPD_SEL (3 << 12)
> +#define DPTX_HPD_DEL (2 << 12)
> +#define DPTX_HPD_SEL_MASK (3 << 28)
> +
> +#define PHY_MODE_SET_TIMEOUT 1000000
> +
> +#define MODE_DISCONNECT 0
> +#define MODE_UFP_USB BIT(0)
> +#define MODE_DFP_USB BIT(1)
> +#define MODE_DFP_DP BIT(2)
> +
> +struct usb3phy_reg {
> + u32 offset;
> + u32 enable_bit;
> + u32 write_enable;
> +};
> +
> +struct rockchip_usb3phy_port_cfg {
> + struct usb3phy_reg typec_conn_dir;
> + struct usb3phy_reg usb3tousb2_en;
> + struct usb3phy_reg external_psm;
> + struct usb3phy_reg pipe_status;
> + struct usb3phy_reg uphy_dp_sel;
> +};
> +
> +struct rockchip_typec_phy {
> + struct device *dev;
> + void __iomem *base;
> + struct extcon_dev *extcon;
> + struct phy *phy;
> + struct regmap *grf_regs;
> + struct clk *clk_core;
> + struct clk *clk_ref;
> + struct reset_control *phy_rst;
> + struct reset_control *pipe_rst;
> + struct reset_control *uphy_rst;
> + struct rockchip_usb3phy_port_cfg port_cfgs;
> +
> + /* to receive notifier from PD */
> + struct notifier_block event_nb;
> + struct delayed_work event_wq;
> +
> + bool flip;
> + bool hpd_status;
> + int mode;
> + int map;
> +};
> +
> +struct phy_reg {
> + int value;
> + int addr;
> +};
> +
> +struct phy_reg usb_pll_cfg[] = {
> + {0xf0, CMN_PLL0_VCOCAL_INIT},
> + {0x18, CMN_PLL0_VCOCAL_ITER},
> + {0xd0, CMN_PLL0_INTDIV},
> + {0x4a4a, CMN_PLL0_FRACDIV},
> + {0x34, CMN_PLL0_HIGH_THR},
> + {0x1ee, CMN_PLL0_SS_CTRL1},
> + {0x7f03, CMN_PLL0_SS_CTRL2},
> + {0x20, CMN_PLL0_DSM_DIAG},
> + {0, CMN_DIAG_PLL0_OVRD},
> + {0, CMN_DIAG_PLL0_FBH_OVRD},
> + {0, CMN_DIAG_PLL0_FBL_OVRD},
> + {0x7, CMN_DIAG_PLL0_V2I_TUNE},
> + {0x45, CMN_DIAG_PLL0_CP_TUNE},
> + {0x8, CMN_DIAG_PLL0_LF_PROG},
> +};
> +
> +struct phy_reg dp_pll_cfg[] = {
> + {0xf0, CMN_PLL1_VCOCAL_INIT},
> + {0x18, CMN_PLL1_VCOCAL_ITER},
> + {0x30b9, CMN_PLL1_VCOCAL_START},
> + {0x21c, CMN_PLL1_INTDIV},
> + {0, CMN_PLL1_FRACDIV},
> + {0x5, CMN_PLL1_HIGH_THR},
> + {0x35, CMN_PLL1_SS_CTRL1},
> + {0x7f1e, CMN_PLL1_SS_CTRL2},
> + {0x20, CMN_PLL1_DSM_DIAG},
> + {0, CMN_PLLSM1_USER_DEF_CTRL},
> + {0, CMN_DIAG_PLL1_OVRD},
> + {0, CMN_DIAG_PLL1_FBH_OVRD},
> + {0, CMN_DIAG_PLL1_FBL_OVRD},
> + {0x6, CMN_DIAG_PLL1_V2I_TUNE},
> + {0x45, CMN_DIAG_PLL1_CP_TUNE},
> + {0x8, CMN_DIAG_PLL1_LF_PROG},
> + {0x100, CMN_DIAG_PLL1_PTATIS_TUNE1},
> + {0x7, CMN_DIAG_PLL1_PTATIS_TUNE2},
> + {0x4, CMN_DIAG_PLL1_INCLK_CTRL},
> +};
> +
> +static void tcphy_cfg_24m(struct rockchip_typec_phy *tcphy,
> + u32 num_lanes)
> +{
> + u32 i;
> +
> + /*
> + * cmn_ref_clk_sel = 3, select the 24Mhz for clk parent
> + * cmn_psm_clk_dig_div = 2, set the clk division to 2
> + */
> + writel(0x830, tcphy->base + PMA_CMN_CTRL1);
> + for (i = 0; i < num_lanes; i++) {
> + /*
> + * The following PHY configuration assumes a 24 MHz reference
> + * clock.
> + */
> + writel(0x90, tcphy->base + XCVR_DIAG_LANE_FCM_EN_MGN(i));
> + writel(0x960, tcphy->base + TX_RCVDET_EN_TMR(i));
> + writel(0x30, tcphy->base + TX_RCVDET_ST_TMR(i));
> + }
> +}
> +
> +static void tcphy_cfg_usb_pll(struct rockchip_typec_phy *tcphy)
> +{
> + u32 rdata;
> + u32 i;
> +
> + /*
> + * Selects which PLL clock will be driven on the analog high speed
> + * clock 0: PLL 0 div 1.
> + */
> + rdata = readl(tcphy->base + CMN_DIAG_HSCLK_SEL);
> + writel(rdata & 0xfffc, tcphy->base + CMN_DIAG_HSCLK_SEL);
> +
> + /* load the configuration of PLL0 */
> + for (i = 0; i < ARRAY_SIZE(usb_pll_cfg); i++)
> + writel(usb_pll_cfg[i].value, tcphy->base + usb_pll_cfg[i].addr);
> +}
> +
> +static void tcphy_cfg_dp_pll(struct rockchip_typec_phy *tcphy)
> +{
> + u32 rdata;
> + u32 i;
> +
> + /* set the default mode to RBR */
> + writel(DP_PLL_CLOCK_ENABLE | DP_PLL_ENABLE | DP_PLL_DATA_RATE_RBR,
> + tcphy->base + DP_CLK_CTL);
> +
> + /*
> + * Selects which PLL clock will be driven on the analog high speed
> + * clock 1: PLL 1 div 2.
> + */
> + rdata = readl(tcphy->base + CMN_DIAG_HSCLK_SEL);
> + rdata = (rdata & 0xffcf) | 0x30;
> + writel(rdata, tcphy->base + CMN_DIAG_HSCLK_SEL);
> +
> + /* load the configuration of PLL1 */
> + for (i = 0; i < ARRAY_SIZE(dp_pll_cfg); i++)
> + writel(dp_pll_cfg[i].value, tcphy->base + dp_pll_cfg[i].addr);
> +}
> +
> +static void tcphy_tx_usb_cfg_lane(struct rockchip_typec_phy *tcphy,
> + u32 lane)
> +{
> + writel(0x7799, tcphy->base + TX_PSC_A0(lane));
> + writel(0x7798, tcphy->base + TX_PSC_A1(lane));
> + writel(0x5098, tcphy->base + TX_PSC_A2(lane));
> + writel(0x5098, tcphy->base + TX_PSC_A3(lane));
> + writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_000(lane));
> + writel(0xbf, tcphy->base + XCVR_DIAG_BIDI_CTRL(lane));
> +}
> +
> +static void tcphy_rx_usb_cfg_lane(struct rockchip_typec_phy *tcphy,
> + u32 lane)
> +{
> + writel(0xa6fd, tcphy->base + RX_PSC_A0(lane));
> + writel(0xa6fd, tcphy->base + RX_PSC_A1(lane));
> + writel(0xa410, tcphy->base + RX_PSC_A2(lane));
> + writel(0x2410, tcphy->base + RX_PSC_A3(lane));
> + writel(0x23ff, tcphy->base + RX_PSC_CAL(lane));
> + writel(0x13, tcphy->base + RX_SIGDET_HL_FILT_TMR(lane));
> + writel(0x1004, tcphy->base + RX_DIAG_SIGDET_TUNE(lane));
> + writel(0x2010, tcphy->base + RX_PSC_RDY(lane));
> + writel(0xfb, tcphy->base + XCVR_DIAG_BIDI_CTRL(lane));
> +}
> +
> +static void tcphy_dp_cfg_lane(struct rockchip_typec_phy *tcphy,
> + u32 lane)
> +{
> + u32 rdata;
> +
> + writel(0xbefc, tcphy->base + XCVR_PSM_RCTRL(lane));
> + writel(0x6799, tcphy->base + TX_PSC_A0(lane));
> + writel(0x6798, tcphy->base + TX_PSC_A1(lane));
> + writel(0x98, tcphy->base + TX_PSC_A2(lane));
> + writel(0x98, tcphy->base + TX_PSC_A3(lane));
> +
> + writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_000(lane));
> + writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_001(lane));
> + writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_010(lane));
> + writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_011(lane));
> + writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_100(lane));
> + writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_101(lane));
> + writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_110(lane));
> + writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_111(lane));
> + writel(0, tcphy->base + TX_TXCC_CPOST_MULT_10(lane));
> + writel(0, tcphy->base + TX_TXCC_CPOST_MULT_01(lane));
> + writel(0, tcphy->base + TX_TXCC_CPOST_MULT_00(lane));
> + writel(0, tcphy->base + TX_TXCC_CPOST_MULT_11(lane));
> +
> + writel(0x128, tcphy->base + TX_TXCC_CAL_SCLR_MULT(lane));
> + writel(0x700, tcphy->base + TX_DIAG_TX_DRV(lane));
> +
> + rdata = readl(tcphy->base + XCVR_DIAG_PLLDRC_CTRL(lane));
> + rdata = (rdata & 0x8fff) | 0x6000;
> + writel(rdata, tcphy->base + XCVR_DIAG_PLLDRC_CTRL(lane));
> +}
> +
> +static void tcphy_cfg_pin_assign(struct rockchip_typec_phy *tcphy)
> +{
> + switch (tcphy->map) {
> + case PIN_MAP_A:
> + writel(0x19d5, tcphy->base + PMA_LANE_CFG);
> + break;
> + case PIN_MAP_B:
> + writel(0x1500, tcphy->base + PMA_LANE_CFG);
> + break;
> + case PIN_MAP_C:
> + case PIN_MAP_E:
> + writel(0x51d9, tcphy->base + PMA_LANE_CFG);
> + break;
> + case PIN_MAP_D:
> + case PIN_MAP_F:
> + writel(0x5100, tcphy->base + PMA_LANE_CFG);
> + break;
> + };
> +}
> +
> +static inline int property_enable(struct rockchip_typec_phy *tcphy,
> + const struct usb3phy_reg *reg, bool en)
> +{
> + int mask = 1 << reg->write_enable;
> + int val = en << reg->enable_bit;
> +
> + return regmap_write(tcphy->grf_regs, reg->offset, val | mask);
> +}
> +
> +static void tcphy_lanes_config(struct rockchip_typec_phy *tcphy)
> +{
> + struct rockchip_usb3phy_port_cfg *cfg = &tcphy->port_cfgs;
> + u32 i;
> +
> + property_enable(tcphy, &cfg->typec_conn_dir, tcphy->flip);
> +
> + tcphy_cfg_24m(tcphy, 0x4);
> +
> + switch (tcphy->mode) {
> + case MODE_UFP_USB:
> + case MODE_DFP_USB:
> + tcphy_cfg_usb_pll(tcphy);
> + if (tcphy->flip) {
> + tcphy_tx_usb_cfg_lane(tcphy, 3);
> + tcphy_rx_usb_cfg_lane(tcphy, 2);
> + } else {
> + tcphy_tx_usb_cfg_lane(tcphy, 0);
> + tcphy_rx_usb_cfg_lane(tcphy, 1);
> + }
> + break;
> + case MODE_DFP_DP:
> + tcphy_cfg_dp_pll(tcphy);
> + for (i = 0; i < 4; i++)
> + tcphy_dp_cfg_lane(tcphy, i);
> + break;
> + case MODE_DFP_USB | MODE_DFP_DP:
> + tcphy_cfg_usb_pll(tcphy);
> + tcphy_cfg_dp_pll(tcphy);
> + if (tcphy->flip) {
> + tcphy_tx_usb_cfg_lane(tcphy, 3);
> + tcphy_rx_usb_cfg_lane(tcphy, 2);
> + tcphy_dp_cfg_lane(tcphy, 0);
> + tcphy_dp_cfg_lane(tcphy, 1);
> + } else {
> + tcphy_tx_usb_cfg_lane(tcphy, 0);
> + tcphy_rx_usb_cfg_lane(tcphy, 1);
> + tcphy_dp_cfg_lane(tcphy, 2);
> + tcphy_dp_cfg_lane(tcphy, 3);
> + }
> + break;
> + }
> +}
> +
> +static void tcphy_dp_aux_calibration(struct rockchip_typec_phy *tcphy)
> +{
> + int rdata, rdata2, val;
> +
> + /* disable txda_cal_latch_en for rewrite the calibration values */
> + rdata = readl(tcphy->base + TX_ANA_CTRL_REG_1);
> + val = rdata & 0xdfff;
> + writel(val, tcphy->base + TX_ANA_CTRL_REG_1);
> +
> + /*
> + * read a resistor calibration code from CMN_TXPUCAL_CTRL[6:0] and
> + * write it to TX_DIG_CTRL_REG_2[6:0], and delay 1ms to make sure it
> + * works.
> + */
> + rdata = readl(tcphy->base + TX_DIG_CTRL_REG_2);
> + rdata = rdata & 0xffc0;
> +
> + rdata2 = readl(tcphy->base + CMN_TXPUCAL_CTRL);
> + rdata2 = rdata2 & 0x3f;
> +
> + val = rdata | rdata2;
> + writel(val, tcphy->base + TX_DIG_CTRL_REG_2);
> + usleep_range(1000, 1050);
> +
> + /*
> + * Enable signal for latch that sample and holds calibration values.
> + * Activate this signal for 1 clock cycle to sample new calibration
> + * values.
> + */
> + rdata = readl(tcphy->base + TX_ANA_CTRL_REG_1);
> + val = rdata | 0x2000;
> + writel(val, tcphy->base + TX_ANA_CTRL_REG_1);
> + usleep_range(150, 200);
> +
> + /* set TX Voltage Level and TX Deemphasis to 0 */
> + writel(0, tcphy->base + PHY_DP_TX_CTL);
> + /* re-enable decap */
> + writel(0x100, tcphy->base + TX_ANA_CTRL_REG_2);
> + writel(0x300, tcphy->base + TX_ANA_CTRL_REG_2);
> + writel(0x2008, tcphy->base + TX_ANA_CTRL_REG_1);
> + writel(0x2018, tcphy->base + TX_ANA_CTRL_REG_1);
> +
> + writel(0, tcphy->base + TX_ANA_CTRL_REG_5);
> +
> + /*
> + * Programs txda_drv_ldo_prog[15:0], Sets driver LDO
> + * voltage 16'h1001 for DP-AUX-TX and RX
> + */
> + writel(0x1001, tcphy->base + TX_ANA_CTRL_REG_4);
> +
> + /* re-enables Bandgap reference for LDO */
> + writel(0x2098, tcphy->base + TX_ANA_CTRL_REG_1);
> + writel(0x2198, tcphy->base + TX_ANA_CTRL_REG_1);
> +
> + /*
> + * re-enables the transmitter pre-driver, driver data selection MUX,
> + * and receiver detect circuits.
> + */
> + writel(0x301, tcphy->base + TX_ANA_CTRL_REG_2);
> + writel(0x303, tcphy->base + TX_ANA_CTRL_REG_2);
> +
> + /*
> + * Controls auxda_polarity, which selects the polarity of the xcvr
> + * 1'b1 : Reverses the polarity (If TYPEC, Pulls ups aux_p and pull
> + * down aux_m)
> + * 1'b0 : Normal polarity (if TYPE_C, pulls up aux_m and pulls down
> + * aux_p)
> + */
> + if (tcphy->flip)
> + writel(0xa078, tcphy->base + TX_ANA_CTRL_REG_1);
> + else
> + writel(0xb078, tcphy->base + TX_ANA_CTRL_REG_1);
> +
> + writel(0, tcphy->base + TX_ANA_CTRL_REG_3);
> + writel(0, tcphy->base + TX_ANA_CTRL_REG_4);
> + writel(0, tcphy->base + TX_ANA_CTRL_REG_5);
> +
> + /*
> + * Controls low_power_swing_en, set the voltage swing of the driver
> + * to 400mv. The values below are peak to peak (differential) values.
> + */
> + writel(4, tcphy->base + TXDA_COEFF_CALC_CTRL);
> + writel(0, tcphy->base + TXDA_CYA_AUXDA_CYA);
> +
> + /* Controls tx_high_z_tm_en */
> + val = readl(tcphy->base + TX_DIG_CTRL_REG_2);
> + val |= BIT(15);
> + writel(val, tcphy->base + TX_DIG_CTRL_REG_2);
> +}
> +
> +static void tcphy_usb3_init(struct rockchip_typec_phy *tcphy)
> +{
> + struct rockchip_usb3phy_port_cfg *cfg = &tcphy->port_cfgs;
> + const struct usb3phy_reg *reg = &cfg->pipe_status;
> + int timeout;
> + unsigned int val;
> +
> + /* wait TCPHY for pipe ready */
> + for (timeout = 0; timeout < 1000; timeout++) {
> + regmap_read(tcphy->grf_regs, reg->offset, &val);
> + if (!(val & BIT(reg->enable_bit)))
> + return;
> + usleep_range(10, 20);
> + }
> +
> + dev_err(tcphy->dev, "wait pipe ready timeout!\n");
> +}
> +
> +static int tcphy_dp_init(struct rockchip_typec_phy *tcphy)
> +{
> + struct rockchip_usb3phy_port_cfg *cfg = &tcphy->port_cfgs;
> + int ret, val;
> +
> + property_enable(tcphy, &cfg->uphy_dp_sel, 1);
> +
> + ret = readx_poll_timeout(readl, tcphy->base + DP_MODE_CTL,
> + val, val & BIT(6), 1000, PHY_MODE_SET_TIMEOUT);
> + if (ret < 0) {
> + dev_err(tcphy->dev, "failed to wait TCPHY for DP ready\n");
> + return ret;
> + }
> +
> + tcphy_dp_aux_calibration(tcphy);
> +
> + if (tcphy->mode & MODE_DFP_USB)
> + writel(0xc101, tcphy->base + DP_MODE_CTL);
> + else
> + writel(0x0101, tcphy->base + DP_MODE_CTL);
> +
> + ret = readx_poll_timeout(readl, tcphy->base + DP_MODE_CTL,
> + val, val & BIT(4), 1000, PHY_MODE_SET_TIMEOUT);
> + if (ret < 0) {
> + dev_err(tcphy->dev, "failed to wait TCPHY enter A0\n");
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int tcphy_phy_init(struct rockchip_typec_phy *tcphy)
> +{
> + struct rockchip_usb3phy_port_cfg *cfg = &tcphy->port_cfgs;
> + int ret, val;
> +
> + ret = clk_prepare_enable(tcphy->clk_core);
> + if (ret) {
> + dev_err(tcphy->dev, "Failed to prepare_enable core clock\n");
> + return ret;
> + }
> +
> + ret = clk_set_rate(tcphy->clk_core, 50000000);
> + if (ret) {
> + dev_err(tcphy->dev, "set type-c phy core clk rate failed\n");
> + goto clk_ref_failed;
> + }
> +
> + ret = clk_prepare_enable(tcphy->clk_ref);
> + if (ret) {
> + dev_err(tcphy->dev, "Failed to prepare_enable ref clock\n");
> + goto clk_ref_failed;
> + }
> +
> + reset_control_assert(tcphy->uphy_rst);
> + reset_control_assert(tcphy->phy_rst);
> + reset_control_assert(tcphy->pipe_rst);
> +
> + /* select external psm clock */
> + property_enable(tcphy, &cfg->external_psm, 1);
> + property_enable(tcphy, &cfg->usb3tousb2_en, 0);
> +
> + reset_control_deassert(tcphy->uphy_rst);
> +
> + tcphy_lanes_config(tcphy);
> +
> + tcphy_cfg_pin_assign(tcphy);
> +
> + if (tcphy->mode & MODE_DFP_DP) {
> + if (tcphy->mode & MODE_DFP_USB)
> + writel(0xc104, tcphy->base + DP_MODE_CTL);
> + else
> + writel(0x0104, tcphy->base + DP_MODE_CTL);
> + }
> +
> + reset_control_deassert(tcphy->phy_rst);
> +
> + ret = readx_poll_timeout(readl, tcphy->base + PMA_CMN_CTRL1,
> + val, val & CMN_READY, 10,
> + PHY_MODE_SET_TIMEOUT);
> + if (ret < 0) {
> + dev_err(tcphy->dev, "wait pma ready timeout\n");
> + goto timeout_failed;
> + }
> +
> + reset_control_deassert(tcphy->pipe_rst);
> +
> + return 0;
> +
> +timeout_failed:
> + clk_disable_unprepare(tcphy->clk_ref);
> +clk_ref_failed:
> + clk_disable_unprepare(tcphy->clk_core);
> + return ret;
> +}
> +
> +static void tcphy_phy_deinit(struct rockchip_typec_phy *tcphy)
> +{
> + clk_disable_unprepare(tcphy->clk_core);
> + clk_disable_unprepare(tcphy->clk_ref);
> +}
> +
> +static const struct phy_ops rockchip_tcphy_ops = {
> + .owner = THIS_MODULE,
> +};
> +
> +static int tcphy_pd_event(struct notifier_block *nb,
> + unsigned long event, void *priv)
> +{
> + struct rockchip_typec_phy *tcphy;
> + struct extcon_dev *edev = priv;
> + int value = edev->state;
> + int mode;
> + u8 is_plugged, dfp;
> +
> + tcphy = container_of(nb, struct rockchip_typec_phy, event_nb);
> +
> + is_plugged = GET_PLUGGED(value);
> + tcphy->flip = GET_FLIP(value);
> + dfp = GET_DFP(value);
> + tcphy->map = GET_PIN_MAP(value);
> +
> + if (is_plugged) {
> + if (!dfp)
> + mode = MODE_UFP_USB;
> + else if (tcphy->map & (PIN_MAP_B | PIN_MAP_D | PIN_MAP_F))
> + mode = MODE_DFP_USB | MODE_DFP_DP;
> + else if (tcphy->map & (PIN_MAP_A | PIN_MAP_C | PIN_MAP_E))
> + mode = MODE_DFP_DP;
> + else
> + mode = MODE_DFP_USB;
> + } else {
> + mode = MODE_DISCONNECT;
> + }
> +
> + if (tcphy->mode != mode) {
> + tcphy->mode = mode;
> + schedule_delayed_work_on(0, &tcphy->event_wq, 0);
> + }
> +
> + return 0;
> +}
> +
> +static void tcphy_event_wq(struct work_struct *work)
> +{
> + struct rockchip_typec_phy *tcphy;
> + int ret;
> +
> + tcphy = container_of(work, struct rockchip_typec_phy, event_wq.work);
> +
> + if (tcphy->mode == MODE_DISCONNECT) {
> + tcphy_phy_deinit(tcphy);
> + /* remove hpd sign for DP */
> + if (tcphy->hpd_status) {
> + regmap_write(tcphy->grf_regs, GRF_SOC_CON26,
> + DPTX_HPD_SEL_MASK | DPTX_HPD_DEL);
> + tcphy->hpd_status = 0;
> + }
> + } else {
> + ret = tcphy_phy_init(tcphy);
> + if (ret)
> + return;
> +
> + if (tcphy->mode & (MODE_UFP_USB | MODE_DFP_USB))
> + tcphy_usb3_init(tcphy);
> +
> + if (tcphy->mode & MODE_DFP_DP) {
> + ret = tcphy_dp_init(tcphy);
> +
> + /* set hpd sign for DP, if DP phy is ready */
> + if (!ret) {
> + regmap_write(tcphy->grf_regs, GRF_SOC_CON26,
> + DPTX_HPD_SEL_MASK | DPTX_HPD_SEL);
> + tcphy->hpd_status = 1;
> + }
> + }
> + }
> +}
> +
> +static int tcphy_get_param(struct device *dev,
> + struct usb3phy_reg *reg,
> + const char *name)
> +{
> + int ret, buffer[3];
> +
> + ret = of_property_read_u32_array(dev->of_node, name, buffer, 3);
> + if (ret) {
> + dev_err(dev, "Can not parse %s\n", name);
> + return ret;
> + }
> +
> + reg->offset = buffer[0];
> + reg->enable_bit = buffer[1];
> + reg->write_enable = buffer[2];
> + return 0;
> +}
> +
> +static int tcphy_parse_dt(struct rockchip_typec_phy *tcphy,
> + struct device *dev)
> +{
> + struct rockchip_usb3phy_port_cfg *cfg = &tcphy->port_cfgs;
> + int ret;
> +
> + ret = tcphy_get_param(dev, &cfg->typec_conn_dir,
> + "rockchip,typec_conn_dir");
> + if (ret)
> + return ret;
> +
> + ret = tcphy_get_param(dev, &cfg->usb3tousb2_en,
> + "rockchip,usb3tousb2_en");
> + if (ret)
> + return ret;
> +
> + ret = tcphy_get_param(dev, &cfg->external_psm,
> + "rockchip,external_psm");
> + if (ret)
> + return ret;
> +
> + ret = tcphy_get_param(dev, &cfg->pipe_status,
> + "rockchip,pipe_status");
> + if (ret)
> + return ret;
> +
> + ret = tcphy_get_param(dev, &cfg->uphy_dp_sel,
> + "rockchip,uphy_dp_sel");
> + if (ret)
> + return ret;
> +
> + tcphy->grf_regs = syscon_regmap_lookup_by_phandle(dev->of_node,
> + "rockchip,grf");
> + if (IS_ERR(tcphy->grf_regs)) {
> + dev_err(dev, "could not find grf dt node\n");
> + return PTR_ERR(tcphy->grf_regs);
> + }
> +
> + tcphy->clk_core = devm_clk_get(dev, "tcpdcore");
> + if (IS_ERR(tcphy->clk_core)) {
> + dev_err(dev, "could not get uphy core clock\n");
> + return PTR_ERR(tcphy->clk_core);
> + }
> +
> + tcphy->clk_ref = devm_clk_get(dev, "tcpdphy_ref");
> + if (IS_ERR(tcphy->clk_ref)) {
> + dev_err(dev, "could not get uphy ref clock\n");
> + return PTR_ERR(tcphy->clk_ref);
> + }
> +
> + tcphy->phy_rst = devm_reset_control_get(dev, "tcphy");
> + if (IS_ERR(tcphy->phy_rst)) {
> + dev_err(dev, "no phy_rst reset control found\n");
> + return PTR_ERR(tcphy->phy_rst);
> + }
> +
> + tcphy->pipe_rst = devm_reset_control_get(dev, "tcphy_pipe");
> + if (IS_ERR(tcphy->pipe_rst)) {
> + dev_err(dev, "no pipe_rst reset control found\n");
> + return PTR_ERR(tcphy->pipe_rst);
> + }
> +
> + tcphy->uphy_rst = devm_reset_control_get(dev, "uphy_tcphy");
> + if (IS_ERR(tcphy->uphy_rst)) {
> + dev_err(dev, "no uphy_rst reset control found\n");
> + return PTR_ERR(tcphy->uphy_rst);
> + }
> +
> + return 0;
> +}
> +
> +static int rockchip_typec_phy_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct rockchip_typec_phy *tcphy;
> + struct resource *res;
> + struct phy_provider *phy_provider;
> + int ret;
> +
> + tcphy = devm_kzalloc(dev, sizeof(*tcphy), GFP_KERNEL);
> + if (!tcphy)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + tcphy->base = devm_ioremap_resource(dev, res);
> + if (IS_ERR(tcphy->base)) {
> + dev_err(dev, "failed to remap phy regs\n");
> + return PTR_ERR(tcphy->base);
> + }
> +
> + tcphy_parse_dt(tcphy, dev);
> +
> + tcphy->dev = dev;
> + platform_set_drvdata(pdev, tcphy);
> +
> + tcphy->mode = MODE_DISCONNECT;
> +
> + tcphy->phy = devm_phy_create(dev, NULL, &rockchip_tcphy_ops);
> + if (IS_ERR(tcphy->phy)) {
> + dev_err(dev, "failed to create Tepy-c PHY\n");
> + return PTR_ERR(tcphy->phy);
> + }
> +
> + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> + if (IS_ERR(phy_provider)) {
> + dev_err(dev, "Failed to register phy provider\n");
> + return PTR_ERR(phy_provider);
> + }
> +
> + tcphy->extcon = extcon_get_edev_by_phandle(dev, 0);
> + if (IS_ERR(tcphy->extcon)) {
> + if (PTR_ERR(tcphy->extcon) != -EPROBE_DEFER)
> + dev_err(dev, "Invalid or missing extcon\n");
> + return PTR_ERR(tcphy->extcon);
> + }
> +
> + tcphy->event_nb.notifier_call = tcphy_pd_event;
> + INIT_DELAYED_WORK(&tcphy->event_wq, tcphy_event_wq);
> + ret = extcon_register_notifier(tcphy->extcon, EXTCON_USB,
> + &tcphy->event_nb);
> + if (ret) {
> + dev_err(dev, "regitster notifer failed\n");
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int rockchip_typec_phy_remove(struct platform_device *pdev)
> +{
> + struct rockchip_typec_phy *tcphy = platform_get_drvdata(pdev);
> +
> + extcon_unregister_notifier(tcphy->extcon, EXTCON_USB,
> + &tcphy->event_nb);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id rockchip_typec_phy_dt_ids[] = {
> + { .compatible = "rockchip,rk3399-typec-phy" },
> + {}
> +};
> +
> +MODULE_DEVICE_TABLE(of, rockchip_typec_phy_dt_ids);
> +
> +static struct platform_driver rockchip_typec_phy_driver = {
> + .probe = rockchip_typec_phy_probe,
> + .remove = rockchip_typec_phy_remove,
> + .driver = {
> + .name = "rockchip-typec-phy",
> + .of_match_table = rockchip_typec_phy_dt_ids,
> + },
> +};
> +
> +module_platform_driver(rockchip_typec_phy_driver);
> +
> +MODULE_AUTHOR("Chris Zhong <zyw@...k-chips.com>");
> +MODULE_AUTHOR("Kever Yang <kever.yang@...k-chips.com>");
> +MODULE_DESCRIPTION("Rockchip USB TYPE-C PHY driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/include/linux/phy/phy-rockchip-typec.h b/include/linux/phy/phy-rockchip-typec.h
> new file mode 100644
> index 0000000..acdd8cb
> --- /dev/null
> +++ b/include/linux/phy/phy-rockchip-typec.h
> @@ -0,0 +1,20 @@
> +#ifndef PHY_ROCKCHIP_TYPEC_H_
> +#define PHY_ROCKCHIP_TYPEC_H_
> +
> +#define PIN_MAP_A BIT(0)
> +#define PIN_MAP_B BIT(1)
> +#define PIN_MAP_C BIT(2)
> +#define PIN_MAP_D BIT(3)
> +#define PIN_MAP_E BIT(4)
> +#define PIN_MAP_F BIT(5)
> +
> +#define SET_PIN_MAP(x) (((x) & 0xff) << 24)
> +#define SET_FLIP(x) (((x) & 0xff) << 16)
> +#define SET_DFP(x) (((x) & 0xff) << 8)
> +#define SET_PLUGGED(x) ((x) & 0xff)
> +#define GET_PIN_MAP(x) (((x) >> 24) & 0xff)
> +#define GET_FLIP(x) (((x) >> 16) & 0xff)
> +#define GET_DFP(x) (((x) >> 8) & 0xff)
> +#define GET_PLUGGED(x) ((x) & 0xff)
> +
> +#endif
Reviewed-by: Kever Yang <kever.yang@...k-chips.com>
Thanks,
- Kever
Powered by blists - more mailing lists