linux-kernel - [PATCH 0/10] x86/tsc: fast calibration updates

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Message-Id: <20160617052252.25991-1-lenb@kernel.org>
Date:	Fri, 17 Jun 2016 01:22:42 -0400
From:	Len Brown <lenb@...nel.org>
To:	x86@...nel.org
Cc:	linux-kernel@...r.kernel.org
Subject: [PATCH 0/10] x86/tsc: fast calibration updates

Originally I wrote this series to increase TSC calibration
accuracy and speed, but it now it also includes
changes that are mandatory for some systems to work correctly.
In particular, the Airmont table entires are already being
used in products, and some BXT steppings will fail without
the check added by patch 10.

LKP tested this patch series in early April on top of 4.6-rc1
and found a failure.  That failure has been fixed
upstream in 4.6 by commit 886123fb3a86
(x86/tsc: Read all ratio bits from MSR_PLATFORM_INFO)

So I have re-based the series on top of 4.7-rc3
to take advantage of that fix, as well as to handle
3 merge conflicts due to intervening upstream commits.

The series now starts by reverting e2724e9d9692
(x86/tsc: Add missing Cherrytrail frequency to the table)
as that is replaced by the more correct and complete
"x86 tsc_msr: Add Airmont reference clock values" in this series.

Also, syntax changes were necessary to both
"x86 tsc: enumerate SKL cpu_khz and tsc_khz via CPUID"
"x86 tsc: enumerate BXT tsc_khz via CPUID"
in response to cleanups recently applied upstream to tsc.c

[PATCH 01/10] Revert "x86/tsc: Add missing Cherrytrail frequency to
[PATCH 02/10] x86 tsc_msr: Identify Intel-specific code
[PATCH 03/10] x86 tsc_msr: Remove debugging messages
[PATCH 04/10] x86 tsc_msr: Update comments, expand definitions
[PATCH 05/10] x86 tsc_msr: Correct Silvermont reference clock values
[PATCH 06/10] x86 tsc_msr: Add Airmont reference clock values
[PATCH 07/10] x86 tsc_msr: Extend to include Intel Core Architecture
[PATCH 08/10] x86 tsc_msr: Remove irqoff around MSR-based TSC
[PATCH 09/10] x86 tsc: enumerate SKL cpu_khz and tsc_khz via CPUID
[PATCH 10/10] x86 tsc: enumerate BXT tsc_khz via CPUID