linux-kernel - Re: [PATCH v2 08/11] Documentation: phy: Let the rockchip eMMC PHY get an exported card clock

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Message-ID: <1549570.EU63ODFg79@diego>
Date:	Sat, 18 Jun 2016 23:48:15 +0200
From:	Heiko Stübner <heiko@...ech.de>
To:	Douglas Anderson <dianders@...omium.org>
Cc:	ulf.hansson@...aro.org, kishon@...com, robh+dt@...nel.org,
	shawn.lin@...k-chips.com, xzy.xu@...k-chips.com,
	briannorris@...omium.org, adrian.hunter@...el.com,
	linux-rockchip@...ts.infradead.org, linux-mmc@...r.kernel.org,
	devicetree@...r.kernel.org, pawel.moll@....com,
	mark.rutland@....com, ijc+devicetree@...lion.org.uk,
	galak@...eaurora.org, linux-arm-kernel@...ts.infradead.org,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 08/11] Documentation: phy: Let the rockchip eMMC PHY get an exported card clock

Am Montag, 13. Juni 2016, 16:04:32 schrieb Douglas Anderson:
> As of an earlier change in this series ("Documentation: mmc:
> sdhci-of-arasan: Add ability to export card clock") the SDHCI driver
> used on Rockchip SoCs can now expose its clock.  Let's now specify that
> the PHY can use it.
> 
> Letting the PHY get access to this clock means it can adjust
> phyctrl_frqsel field appropriately.  Although the Rockchip PHY appears
> slightly different than the reference Arasan one, you can see that the
> Arasan datasheet [1] had it defined as:
>   Select the frequency range of DLL operation:
>   3b'000 => 200MHz to 170 MHz
>   3b'001 => 170MHz to 140 MHz
>   3b'010 => 140MHz to 110 MHz
>   3b'011 => 110MHz to 80MHz
>   3b'100 => 80MHz to 50 MHz
>   3b'101 => 275Mhz to 250MHz
>   3b'110 => 250MHz to 225MHz
>   3b'111 => 225MHz to 200MHz
> 
> On the Rockchip version of the PHY we have less granularity but the idea
> is the same.
> 
> [1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf
> 
> Signed-off-by: Douglas Anderson <dianders@...omium.org>

Reviewed-by: Heiko Stuebner <heiko@...ech.de>