linux-kernel - Re: [PATCH v2 08/11] Documentation: phy: Let the rockchip eMMC PHY get an exported card clock

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <5767E9C3.40009@ti.com>
Date:	Mon, 20 Jun 2016 18:34:03 +0530
From:	Kishon Vijay Abraham I <kishon@...com>
To:	Douglas Anderson <dianders@...omium.org>, <ulf.hansson@...aro.org>,
	Heiko Stuebner <heiko@...ech.de>, <robh+dt@...nel.org>
CC:	<shawn.lin@...k-chips.com>, <xzy.xu@...k-chips.com>,
	<briannorris@...omium.org>, <adrian.hunter@...el.com>,
	<linux-rockchip@...ts.infradead.org>, <linux-mmc@...r.kernel.org>,
	<devicetree@...r.kernel.org>, <pawel.moll@....com>,
	<mark.rutland@....com>, <ijc+devicetree@...lion.org.uk>,
	<galak@...eaurora.org>, <linux-arm-kernel@...ts.infradead.org>,
	<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 08/11] Documentation: phy: Let the rockchip eMMC PHY
 get an exported card clock



On Tuesday 14 June 2016 04:34 AM, Douglas Anderson wrote:
> As of an earlier change in this series ("Documentation: mmc:
> sdhci-of-arasan: Add ability to export card clock") the SDHCI driver
> used on Rockchip SoCs can now expose its clock.  Let's now specify that
> the PHY can use it.
> 
> Letting the PHY get access to this clock means it can adjust
> phyctrl_frqsel field appropriately.  Although the Rockchip PHY appears
> slightly different than the reference Arasan one, you can see that the
> Arasan datasheet [1] had it defined as:
>   Select the frequency range of DLL operation:
>   3b'000 => 200MHz to 170 MHz
>   3b'001 => 170MHz to 140 MHz
>   3b'010 => 140MHz to 110 MHz
>   3b'011 => 110MHz to 80MHz
>   3b'100 => 80MHz to 50 MHz
>   3b'101 => 275Mhz to 250MHz
>   3b'110 => 250MHz to 225MHz
>   3b'111 => 225MHz to 200MHz
> 
> On the Rockchip version of the PHY we have less granularity but the idea
> is the same.
> 
> [1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf
> 
> Signed-off-by: Douglas Anderson <dianders@...omium.org>

Acked-by: Kishon Vijay Abraham I <kishon@...com>
> ---
> Changes in v2:
> - List out clocks and clock names (Rob)
> 
>  Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt
> index 555cb0f40690..e3ea55763b0a 100644
> --- a/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt
> +++ b/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt
> @@ -7,6 +7,13 @@ Required properties:
>   - reg: PHY register address offset and length in "general
>     register files"
>  
> +Optional clocks using the clock bindings (see ../clock/clock-bindings.txt),
> +specified by name:
> + - clock-names: Should contain "emmcclk".  Although this is listed as optional
> +		(because most boards can get basic functionality without having
> +		access to it), it is strongly suggested.
> + - clocks: Should have a phandle to the card clock exported by the SDHCI driver.
> +
>  Example:
>  
>  
> @@ -20,6 +27,8 @@ grf: syscon@...70000 {
>  	emmcphy: phy@...0 {
>  		compatible = "rockchip,rk3399-emmc-phy";
>  		reg = <0xf780 0x20>;
> +		clocks = <&sdhci>;
> +		clock-names = "emmcclk";
>  		#phy-cells = <0>;
>  	};
>  };
>