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Message-ID: <5769BEF0.4040902@ti.com>
Date: Tue, 21 Jun 2016 17:25:52 -0500
From: Suman Anna <s-anna@...com>
To: Keerthy <j-keerthy@...com>, <rnayak@...eaurora.org>,
<tony@...mide.com>
CC: <linux-omap@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<t-kristo@...com>, <afzal@...com>, <d-gerlach@...com>,
<paul@...an.com>, <linux@...linux.org.uk>
Subject: Re: [PATCH] ARM: AM33xx: PRM: Remove wrongly defined RSTST offset for
PER Domain
Hi Keerthy,
On 06/21/2016 05:08 AM, Keerthy wrote:
> As per the TRM: http://www.ti.com/lit/ug/spruh73m/spruh73m.pdf
> offset 0x4 is reserved for PRM_PER. Hence removing the wrongly
> defined address offset.
Thanks for the patch. These macros are not used anywhere, so it should
be safe to remove these. I have tested this patch with an off-tree PRUSS
driver releasing the reset, it works as expected without throwing any
issues.
That said, the current omap_hwmod code assumes default rstst_offs and
st_shift and tries to still write some value into the RSTCTRL register
in am33xx_prm_deassert_hardreset(), but it didn't have any side-affects
though on AM33xx. This is what affected the AM437x due to incorrect
RSTST offset value. That behavior is independent of this patch though.
Tested-by: Suman Anna <s-anna@...com>
regards
Suman
> Signed-off-by: Keerthy <j-keerthy@...com>
> ---
> arch/arm/mach-omap2/prm33xx.h | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/prm33xx.h b/arch/arm/mach-omap2/prm33xx.h
> index 2bc4ec5..66302c6 100644
> --- a/arch/arm/mach-omap2/prm33xx.h
> +++ b/arch/arm/mach-omap2/prm33xx.h
> @@ -52,8 +52,6 @@
> /* PRM.PER_PRM register offsets */
> #define AM33XX_RM_PER_RSTCTRL_OFFSET 0x0000
> #define AM33XX_RM_PER_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0000)
> -#define AM33XX_RM_PER_RSTST_OFFSET 0x0004
> -#define AM33XX_RM_PER_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0004)
> #define AM33XX_PM_PER_PWRSTST_OFFSET 0x0008
> #define AM33XX_PM_PER_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0008)
> #define AM33XX_PM_PER_PWRSTCTRL_OFFSET 0x000c
>
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