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Message-ID: <1466596043-27262-3-git-send-email-ldewangan@nvidia.com>
Date: Wed, 22 Jun 2016 17:17:20 +0530
From: Laxman Dewangan <ldewangan@...dia.com>
To: <thierry.reding@...il.com>, <robh+dt@...nel.org>,
<swarren@...dotorg.org>, <gnurou@...il.com>
CC: <linux-pwm@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-tegra@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
"Victor(Weiguo) Pan" <wpan@...dia.com>,
Laxman Dewangan <ldewangan@...dia.com>
Subject: [PATCH 2/5] pwm: tegra: Allow 100% duty cycle
From: "Victor(Weiguo) Pan" <wpan@...dia.com>
To get 100% duty cycle (always high), pulse width needs to be
set to 256.
Signed-off-by: Victor(Weiguo) Pan <wpan@...dia.com>
Signed-off-by: Laxman Dewangan <ldewangan@...dia.com>
---
drivers/pwm/pwm-tegra.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
index 71b9c4d..575ca8e 100644
--- a/drivers/pwm/pwm-tegra.c
+++ b/drivers/pwm/pwm-tegra.c
@@ -79,7 +79,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
* per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the
* nearest integer during division.
*/
- c = duty_ns * ((1 << PWM_DUTY_WIDTH) - 1) + period_ns / 2;
+ c = duty_ns * (1 << PWM_DUTY_WIDTH) + period_ns / 2;
do_div(c, period_ns);
val = (u32)c << PWM_DUTY_SHIFT;
--
2.1.4
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