linux-kernel - Re: [PATCH v4 2/3] x86/platform/p2sb: New Primary to Sideband bridge support driver for Intel SOC's

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Message-ID: <CACRpkdZ_RNr4tkwQn6u1sE=PqXMHC-jZA0MO=OijjvS7E+M2Lg@mail.gmail.com>
Date:	Thu, 23 Jun 2016 10:45:01 +0200
From:	Linus Walleij <linus.walleij@...aro.org>
To:	Tan Jui Nee <jui.nee.tan@...el.com>
Cc:	Mika Westerberg <mika.westerberg@...ux.intel.com>,
	Heikki Krogerus <heikki.krogerus@...ux.intel.com>,
	Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
	Thomas Gleixner <tglx@...utronix.de>,
	Ingo Molnar <mingo@...hat.com>,
	"H. Peter Anvin" <hpa@...or.com>, x86@...nel.org,
	"ptyser@...-inc.com" <ptyser@...-inc.com>,
	Lee Jones <lee.jones@...aro.org>,
	"linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	jonathan.yong@...el.com, ong.hock.yu@...el.com,
	weifeng.voon@...el.com, wan.ahmad.zainie.wan.mohamad@...el.com
Subject: Re: [PATCH v4 2/3] x86/platform/p2sb: New Primary to Sideband bridge
 support driver for Intel SOC's

On Tue, Jun 21, 2016 at 7:10 AM, Tan Jui Nee <jui.nee.tan@...el.com> wrote:

> From: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
>
> There is already one and at least one more user coming which
> require an access to Primary to Sideband bridge (P2SB) in order
> to get IO or MMIO bar hidden by BIOS.
> Create a driver to access P2SB for x86 devices.
>
> Signed-off-by: Yong, Jonathan <jonathan.yong@...el.com>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
> ---
> Changes in V4:
>         - Move Kconfig option CONFIG_X86_INTEL_NON_ACPI from
>           [PATCH 2/3] x86/platform/p2sb: New Primary to Sideband bridge support driver for Intel SOC's
>           to
>           [PATCH 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake GPIO pinctrl in non-ACPI system
>           since the config is used in latter patch.

Waiting for a respin in accordance with Mika's comments.

You don't need to resend patch 1/3 it is already applied.

Yours,
Linus Walleij