linux-kernel - Re: [PATCH v2 1/3] irqchip: exynos_combiner: fixup reg access on be

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Message-ID: <20160623182522.GI9922@io.lakedaemon.net>
Date:	Thu, 23 Jun 2016 18:25:22 +0000
From:	Jason Cooper <jason@...edaemon.net>
To:	Matthew Leach <matthew@...tleach.net>
Cc:	Krzysztof Kozlowski <k.kozlowski@...sung.com>,
	Ben Dooks <ben.dooks@...ethink.co.uk>,
	linux-samsung-soc@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
	Thomas Gleixner <tglx@...utronix.de>,
	Marc Zyngier <marc.zyngier@....com>,
	Kukjin Kim <kgene@...nel.org>
Subject: Re: [PATCH v2 1/3] irqchip: exynos_combiner: fixup reg access on be

Matt, Ben,

Both of you submitted similar patches for the same driver, same purpose.
Since Ben's hit my inbox first, I'll take his.

thx,

Jason.

On Wed, Jun 22, 2016 at 05:57:01PM +0100, Matthew Leach wrote:
> Use the byte-order aware big endian accessors, allowing for kernels
> running under big-endian.
> 
> Signed-off-by: Matthew Leach <matthew@...tleach.net>
> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@...sung.com>
> ---
> CC: Thomas Gleixner <tglx@...utronix.de>
> CC: Jason Cooper <jason@...edaemon.net>
> CC: Marc Zyngier <marc.zyngier@....com>
> CC: Kukjin Kim <kgene@...nel.org>
> CC: Krzysztof Kozlowski <k.kozlowski@...sung.com>
> CC: linux-kernel@...r.kernel.org
> CC: linux-arm-kernel@...ts.infradead.org
> CC: linux-samsung-soc@...r.kernel.org
> ---
>  drivers/irqchip/exynos-combiner.c | 18 +++++++++---------
>  1 file changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/irqchip/exynos-combiner.c b/drivers/irqchip/exynos-combiner.c
> index ead15be..97ae34c 100644
> --- a/drivers/irqchip/exynos-combiner.c
> +++ b/drivers/irqchip/exynos-combiner.c
> @@ -55,14 +55,14 @@ static void combiner_mask_irq(struct irq_data *data)
>  {
>  	u32 mask = 1 << (data->hwirq % 32);
>  
> -	__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
> +	writel_relaxed(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
>  }
>  
>  static void combiner_unmask_irq(struct irq_data *data)
>  {
>  	u32 mask = 1 << (data->hwirq % 32);
>  
> -	__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
> +	writel_relaxed(mask, combiner_base(data) + COMBINER_ENABLE_SET);
>  }
>  
>  static void combiner_handle_cascade_irq(struct irq_desc *desc)
> @@ -75,7 +75,7 @@ static void combiner_handle_cascade_irq(struct irq_desc *desc)
>  	chained_irq_enter(chip, desc);
>  
>  	spin_lock(&irq_controller_lock);
> -	status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
> +	status = readl_relaxed(chip_data->base + COMBINER_INT_STATUS);
>  	spin_unlock(&irq_controller_lock);
>  	status &= chip_data->irq_mask;
>  
> @@ -135,7 +135,7 @@ static void __init combiner_init_one(struct combiner_chip_data *combiner_data,
>  	combiner_data->parent_irq = irq;
>  
>  	/* Disable all interrupts */
> -	__raw_writel(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR);
> +	writel_relaxed(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR);
>  }
>  
>  static int combiner_irq_domain_xlate(struct irq_domain *d,
> @@ -218,7 +218,7 @@ static int combiner_suspend(void)
>  
>  	for (i = 0; i < max_nr; i++)
>  		combiner_data[i].pm_save =
> -			__raw_readl(combiner_data[i].base + COMBINER_ENABLE_SET);
> +			readl_relaxed(combiner_data[i].base + COMBINER_ENABLE_SET);
>  
>  	return 0;
>  }
> @@ -235,10 +235,10 @@ static void combiner_resume(void)
>  	int i;
>  
>  	for (i = 0; i < max_nr; i++) {
> -		__raw_writel(combiner_data[i].irq_mask,
> -			     combiner_data[i].base + COMBINER_ENABLE_CLEAR);
> -		__raw_writel(combiner_data[i].pm_save,
> -			     combiner_data[i].base + COMBINER_ENABLE_SET);
> +		writel_relaxed(combiner_data[i].irq_mask,
> +			       combiner_data[i].base + COMBINER_ENABLE_CLEAR);
> +		writel_relaxed(combiner_data[i].pm_save,
> +			       combiner_data[i].base + COMBINER_ENABLE_SET);
>  	}
>  }
>  
> -- 
> 2.8.3
>