linux-kernel - Re: [PATCH] ARM: sti: Implement dummy L2 cache's write

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Message-ID: <20160628094914.GI1041@n2100.armlinux.org.uk>
Date:	Tue, 28 Jun 2016 10:49:14 +0100
From:	Russell King - ARM Linux <linux@...linux.org.uk>
To:	patrice.chotard@...com
Cc:	linux-arm-kernel@...ts.infradead.org, kernel@...inux.com,
	linux-kernel@...r.kernel.org, peter.griffin@...aro.org,
	lee.jones@...aro.org
Subject: Re: [PATCH] ARM: sti: Implement dummy L2 cache's write_sec

On Tue, Jun 28, 2016 at 11:40:37AM +0200, patrice.chotard@...com wrote:
> From: Patrice Chotard <patrice.chotard@...com>
> 
> This patch implements the write_sec callback that handle PL310
> secure registers writes.
> This callback is just a stub for now, to avoid system crash.
> Later, it could handle SMC calls so that TZ handles the needed writes.

Is there much point having the L2 cache DT node enabled if you have
no support for the writes, which are required for the hardware to be
enabled?

-- 
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