linux-kernel - Re: [PATCH 2/2] arm64: dts: rockchip: support the pmu node for rk3399

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Message-ID: <20160701102612.GB22953@leverpostej>
Date:	Fri, 1 Jul 2016 11:26:12 +0100
From:	Mark Rutland <mark.rutland@....com>
To:	Caesar Wang <wxt@...k-chips.com>, marc.zyngier@....com
Cc:	Heiko Stuebner <heiko@...ech.de>, dianders@...omium.org,
	Will Deacon <will.deacon@....com>, briannorris@...gle.com,
	linux-rockchip@...ts.infradead.org, cf@...k-chips.com,
	huangtao@...k-chips.com, jay.xu@...k-chips.com,
	linux-arm-kernel@...ts.infradead.org,
	Rob Herring <robh+dt@...nel.org>,
	Catalin Marinas <catalin.marinas@....com>,
	Brian Norris <briannorris@...omium.org>,
	Masahiro Yamada <yamada.masahiro@...ionext.com>,
	David Wu <david.wu@...k-chips.com>, devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/2] arm64: dts: rockchip: support the pmu node for rk3399

On Fri, Jul 01, 2016 at 03:36:10PM +0800, Caesar Wang wrote:
> As the Marc posted the patches [0] to support Partitioning per-cpu
> interrupts. Let's add this patch to match it on rk3399 SoCs.
> 
> [0]:
> https://lkml.org/lkml/2016/4/11/182

The core IRQ support is merged, but it's worth noting that the perf code
doesn't use it yet. So we still need a patch adding support to the perf
code before we can change the dts.

I think Marc had a prototype of that somewhere.

Marc?

> Signed-off-by: Caesar Wang <wxt@...k-chips.com>
> Cc: Heiko Stuebner <heiko@...ech.de>
> Cc: Will Deacon <will.deacon@....com>
> Cc: Marc Zyngier <marc.zyngier@....com>
> CC: linux-arm-kernel@...ts.infradead.org
> 
> ---
> 
>  arch/arm64/boot/dts/rockchip/rk3399.dtsi | 26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> index 8f0a069..b260f62 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> @@ -165,6 +165,22 @@
>  			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
>  	};
>  
> +	pmu_a53 {
> +		compatible = "arm,cortex-a53-pmu";
> +		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>;
> +		interrupt-affinity = <&cpu_l0>,
> +				     <&cpu_l1>,
> +				     <&cpu_l2>,
> +				     <&cpu_l3>;
> +	};

I'm not keen on having to redundantly describe the affinity in
interrupt-affinity and the partition's affinity property. Those will
almost certainly be out-of-sync in some DTs, and it'll be very painful
to deal with.

I think that for partitioned PPIs the PMU driver should use the affinity
from the PPI, and not have an interrupt-affinity property. Hopefully
that's relatively simple to handle.

Thanks,
Mark.

> +
> +	pmu_a72 {
> +		compatible = "arm,cortex-a72-pmu";
> +		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>;
> +		interrupt-affinity = <&cpu_b0>,
> +				     <&cpu_b1>;
> +	};
> +
>  	xin24m: xin24m {
>  		compatible = "fixed-clock";
>  		clock-frequency = <24000000>;
> @@ -296,6 +312,16 @@
>  			msi-controller;
>  			reg = <0x0 0xfee20000 0x0 0x20000>;
>  		};
> +
> +		ppi-partitions {
> +			part0: interrupt-partition-0 {
> +				affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
> +			};
> +
> +			part1: interrupt-partition-1 {
> +				affinity = <&cpu_b0 &cpu_b1>;
> +			};
> +		};
>  	};
>  
>  	i2c1: i2c@...10000 {
> -- 
> 1.9.1
>