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Date: Thu, 30 Jun 2016 18:50:21 -0700 From: Nadav Amit <nadav.amit@...il.com> To: Dave Hansen <dave@...1.net> Cc: LKML <linux-kernel@...r.kernel.org>, x86@...nel.org, linux-mm@...ck.org, torvalds@...ux-foundation.org, akpm@...ux-foundation.org, bp@...en8.de, ak@...ux.intel.com, mhocko@...e.com, dave.hansen@...ux.intel.com Subject: Re: [PATCH 6/6] x86: Fix stray A/D bit setting into non-present PTEs Dave Hansen <dave@...1.net> wrote: > +pte_t ptep_clear_flush(struct vm_area_struct *vma, unsigned long address, > + pte_t *ptep) > +{ > + struct mm_struct *mm = vma->vm_mm; > + pte_t pte; > + > + pte = ptep_get_and_clear(mm, address, ptep); > + if (pte_accessible(mm, pte)) { > + flush_tlb_page(vma, address); > + /* > + * Ensure that the compiler orders our set_pte() > + * after the flush_tlb_page() no matter what. > + */ > + barrier(); I don’t think such a barrier (after remote TLB flush) is needed. Eventually, if a remote flush takes place, you get csd_lock_wait() to be called, and then smp_rmb() is called (which is essentially a barrier() call on x86). Regards, Nadav
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