linux-kernel - Re: [PATCH] cacheinfo: Introduce cache id

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Message-ID: <20160701165041.GA18186@intel.com>
Date:	Fri, 1 Jul 2016 09:50:41 -0700
From:	"Luck, Tony" <tony.luck@...el.com>
To:	Borislav Petkov <bp@...e.de>
Cc:	Fenghua Yu <fenghua.yu@...el.com>,
	Thomas Gleixner <tglx@...utronix.de>,
	Ingo Molnar <mingo@...e.hu>,
	"H. Peter Anvin" <h.peter.anvin@...el.com>,
	Peter Zijlstra <peterz@...radead.org>,
	Stephane Eranian <eranian@...gle.com>,
	Ravi V Shankar <ravi.v.shankar@...el.com>,
	Vikas Shivappa <vikas.shivappa@...ux.intel.com>,
	linux-kernel <linux-kernel@...r.kernel.org>, x86 <x86@...nel.org>
Subject: Re: [PATCH] cacheinfo: Introduce cache id

On Fri, Jul 01, 2016 at 12:21:43PM +0200, Borislav Petkov wrote:
> On Wed, Jun 29, 2016 at 06:56:10PM -0700, Fenghua Yu wrote:
> > From: Fenghua Yu <fenghua.yu@...el.com>
> > 
> > Each cache node is described by cacheinfo and is a unique node across
> 
> What is a cache node?

Clearly not a good name for the concept we are trying to communicate here.
Better suggestions welcome!

Here's the situation.  We have lots of (mostly) independent caches on a system.
The L3 cache (also called LLC - Last Level Cache - in some documentation) is
usually shared by all cpus on a physical socket. The L1 and L2 caches are
typically local to a core, so only shared by the hyperthreads on a core.
But I say "usually" and "typically" because the architecture doesn't require
that. We could have multiple separate L3 caches on a socket with a subset of
cpus assigned to each of them. We could have an L2 cache that is shared by
two or more cores.

/sys/devices/system/cpu/cpu*/cache/index*/shared_cpu_{list,map} allow for
arbitrary sharing schemes and tell you which caches are shared among which
groups of Linux logical cpus.

What we don't have is a *name* for each cache.

CAT (Intel Cache Allocation Technology) allows us to partition caches
on a per task basis. E.g. process A can only use 20% of the L3 cache on
socket0, process B can use 40% (that doesn't overlap with the 20% assigned
to process A - or perhaps does overlap - the feature is quite versatile).
But since caches aren't necessarily mapped to sockets or cores, we need a
name for each cache.

> And since this patch adds the generic functionality and then enables it
> on x86, it should be split into two patches.

Mea culpa.  Fenghua had split this as you suggest, and I said "with just
23 lines added this can be one patch". Sorry Fenghua.

-Tony