linux-kernel - Re: [RFC] mips: Add MXU context switching support

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Message-ID: <alpine.DEB.2.00.1607042317480.4076@tp.orcam.me.uk>
Date:	Mon, 4 Jul 2016 23:30:23 +0100
From:	"Maciej W. Rozycki" <macro@...tec.com>
To:	PrasannaKumar Muralidharan <prasannatsmkumar@...il.com>
CC:	<linux-mips@...ux-mips.org>, <linux-kernel@...r.kernel.org>,
	<adobriyan@...il.com>, <john.stultz@...aro.org>,
	<mguzik@...hat.com>, <athorlton@....com>, <mhocko@...e.com>,
	<ebiederm@...ssion.com>, <gorcunov@...nvz.org>, <luto@...nel.org>,
	<cl@...ux.com>, <serge.hallyn@...ntu.com>, <keescook@...omium.org>,
	<jslaby@...e.cz>, Andrew Morton <akpm@...ux-foundation.org>,
	<f.fainelli@...il.com>, <mingo@...nel.org>,
	<alex.smith@...tec.com>, <markos.chandras@...tec.com>,
	Leonid Yegoshin <Leonid.Yegoshin@...tec.com>,
	<david.daney@...ium.com>, <zhaoxiu.zeng@...il.com>,
	<chenhc@...ote.com>, <Zubair.Kakakhel@...tec.com>,
	James Hogan <james.hogan@...tec.com>, <paul.burton@...tec.com>,
	Ralf Baechle <ralf@...ux-mips.org>
Subject: Re: [RFC] mips: Add MXU context switching support

On Sat, 25 Jun 2016, PrasannaKumar Muralidharan wrote:

> diff --git a/arch/mips/include/asm/mxu.h b/arch/mips/include/asm/mxu.h
> new file mode 100644
> index 0000000..cf77cbd
> --- /dev/null
> +++ b/arch/mips/include/asm/mxu.h
> @@ -0,0 +1,157 @@
> +/*
> + * Copyright (C) Ingenic Semiconductor
> + * File taken from Ingenic Semiconductor's linux repo available in github
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation;  either version 2 of the  License, or (at your
> + * option) any later version.
> + */
> +#ifndef _ASM_MXU_H
> +#define _ASM_MXU_H
> +
> +#include <asm/cpu.h>
> +#include <asm/cpu-features.h>
> +#include <asm/hazards.h>
> +#include <asm/mipsregs.h>
> +
> +static inline void __enable_mxu(void)
> +{
> +	unsigned int register val asm("t0");
> +	val = 3;
> +	asm volatile(".word	0x7008042f\n\t"::"r"(val));

 Can you please document your manually generated machine code, i.e. what 
instruction 0x7008042f actually is?

 Also our convention has been to separate asm operands with spaces, and 
there's no need for a new line or a tab character at the end of an 
inline as GCC will add these automatically as needed, i.e.:

	asm volatile(".word	0x7008042f" : : "r" (val));

Likewise throughout.

> +static inline void __save_mxu(void *tsk_void)
> +{
> +	struct task_struct *tsk = tsk_void;
> +
> +	register unsigned int reg_val asm("t0");
> +
> +	asm volatile(".word	0x7008042e\n\t");
> +	tsk->thread.mxu.xr[0] = reg_val;
> +	asm volatile(".word	0x7008006e\n\t");
> +	tsk->thread.mxu.xr[1] = reg_val;
> +	asm volatile(".word	0x700800ae\n\t");
> +	tsk->thread.mxu.xr[2] = reg_val;
> +	asm volatile(".word	0x700800ee\n\t");
> +	tsk->thread.mxu.xr[3] = reg_val;
> +	asm volatile(".word	0x7008012e\n\t");
> +	tsk->thread.mxu.xr[4] = reg_val;
> +	asm volatile(".word	0x7008016e\n\t");
> +	tsk->thread.mxu.xr[5] = reg_val;
> +	asm volatile(".word	0x700801ae\n\t");
> +	tsk->thread.mxu.xr[6] = reg_val;
> +	asm volatile(".word	0x700801ee\n\t");
> +	tsk->thread.mxu.xr[7] = reg_val;
> +	asm volatile(".word	0x7008022e\n\t");
> +	tsk->thread.mxu.xr[8] = reg_val;
> +	asm volatile(".word	0x7008026e\n\t");
> +	tsk->thread.mxu.xr[9] = reg_val;
> +	asm volatile(".word	0x700802ae\n\t");
> +	tsk->thread.mxu.xr[10] = reg_val;
> +	asm volatile(".word	0x700802ee\n\t");
> +	tsk->thread.mxu.xr[11] = reg_val;
> +	asm volatile(".word	0x7008032e\n\t");
> +	tsk->thread.mxu.xr[12] = reg_val;
> +	asm volatile(".word	0x7008036e\n\t");
> +	tsk->thread.mxu.xr[13] = reg_val;
> +	asm volatile(".word	0x700803ae\n\t");
> +	tsk->thread.mxu.xr[14] = reg_val;
> +	asm volatile(".word	0x700803ee\n\t");
> +	tsk->thread.mxu.xr[15] = reg_val;
> +}

 Not using an output operand with asms here?

  Maciej