lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20160706160525.GA31910@arm.com>
Date:	Wed, 6 Jul 2016 17:05:25 +0100
From:	Will Deacon <will.deacon@....com>
To:	Marc Zyngier <marc.zyngier@....com>
Cc:	linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
	devicetree@...r.kernel.org, linux-rockchip@...ts.infradead.org,
	Heiko Stuebner <heiko@...ech.de>, cf@...k-chips.com,
	huangtao@...k-chips.com, jay.xu@...k-chips.com,
	Caesar Wang <wxt@...k-chips.com>,
	David Wu <david.wu@...k-chips.com>,
	Brian Norris <briannorris@...omium.org>,
	Mark Rutland <mark.rutland@....com>,
	Rob Herring <robh+dt@...nel.org>
Subject: Re: [PATCH v2] drivers/perf: arm-pmu: Handle per-interrupt affinity
 mask

On Wed, Jul 06, 2016 at 03:33:47PM +0100, Marc Zyngier wrote:
> On a big-little system, PMUs can be wired to CPUs using per CPU
> interrups (PPI). In this case, it is important to make sure that
> the enable/disable do happen on the right set of CPUs.
> 
> So instead of relying on the interrupt-affinity property, we can
> use the actual percpu affinity that DT exposes as part of the
> interrupt specifier. The DT binding is also updated to reflect
> the fact that the interrupt-affinity property shouldn't be used
> in that case.
> 
> Signed-off-by: Marc Zyngier <marc.zyngier@....com>
> ---
> * From v1:
>   - propagate the error if irq_get_percpu_devid_partition fails

Thanks, I'll queue this.

Will

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ