linux-kernel - [tip:x86/platform] x86/platform/intel-mid: Extend PWRMU to support Penwell

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Message-ID: <tip-ca22312dc840065206285626829ceed8bb4df88c@git.kernel.org>
Date:	Fri, 8 Jul 2016 05:04:40 -0700
From:	tip-bot for Andy Shevchenko <tipbot@...or.com>
To:	linux-tip-commits@...r.kernel.org
Cc:	hpa@...or.com, andriy.shevchenko@...ux.intel.com,
	torvalds@...ux-foundation.org, linux-kernel@...r.kernel.org,
	peterz@...radead.org, tglx@...utronix.de, mingo@...nel.org,
	bhelgaas@...gle.com
Subject: [tip:x86/platform] x86/platform/intel-mid: Extend PWRMU to support
 Penwell

Commit-ID:  ca22312dc840065206285626829ceed8bb4df88c
Gitweb:     http://git.kernel.org/tip/ca22312dc840065206285626829ceed8bb4df88c
Author:     Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
AuthorDate: Tue, 5 Jul 2016 23:09:08 +0300
Committer:  Ingo Molnar <mingo@...nel.org>
CommitDate: Fri, 8 Jul 2016 11:00:06 +0200

x86/platform/intel-mid: Extend PWRMU to support Penwell

Intel Penwell is one of the first SoCs in Intel MID series. It has slightly
older version of PWRMU IP, though it is compatible with one found on Intel
Tangier. Since we are not using (yet) any advanced stuff in the driver we may
safely re-use what it's done for Intel Tangier for now.

Extend PWRMU driver to support Intel Penwell by adding PCI ID and re-using
existing ->set_initial_state() function.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
Cc: Bjorn Helgaas <bhelgaas@...gle.com>
Cc: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Thomas Gleixner <tglx@...utronix.de>
Link: http://lkml.kernel.org/r/1467749348-100518-2-git-send-email-andriy.shevchenko@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@...nel.org>
---
 arch/x86/platform/intel-mid/pwr.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/x86/platform/intel-mid/pwr.c b/arch/x86/platform/intel-mid/pwr.c
index 59faf05..5bc90dd 100644
--- a/arch/x86/platform/intel-mid/pwr.c
+++ b/arch/x86/platform/intel-mid/pwr.c
@@ -75,6 +75,7 @@
 #define LSS_PWS_BITS		2	/* power state width */
 
 /* Supported device IDs */
+#define PCI_DEVICE_ID_PENWELL	0x0828
 #define PCI_DEVICE_ID_TANGIER	0x11a1
 
 struct mid_pwr_dev {
@@ -354,7 +355,7 @@ static int mid_pwr_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 	return 0;
 }
 
-static int tng_set_initial_state(struct mid_pwr *pwr)
+static int mid_set_initial_state(struct mid_pwr *pwr)
 {
 	unsigned int i, j;
 	int ret;
@@ -397,12 +398,13 @@ static int tng_set_initial_state(struct mid_pwr *pwr)
 	return 0;
 }
 
-static const struct mid_pwr_device_info tng_info = {
-	.set_initial_state = tng_set_initial_state,
+static const struct mid_pwr_device_info mid_info = {
+	.set_initial_state = mid_set_initial_state,
 };
 
 static const struct pci_device_id mid_pwr_pci_ids[] = {
-	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_TANGIER), (kernel_ulong_t)&tng_info },
+	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PENWELL), (kernel_ulong_t)&mid_info },
+	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_TANGIER), (kernel_ulong_t)&mid_info },
 	{}
 };
 MODULE_DEVICE_TABLE(pci, mid_pwr_pci_ids);