[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <3908561D78D1C84285E8C5FCA982C28F3A15599C@ORSMSX114.amr.corp.intel.com>
Date: Fri, 8 Jul 2016 17:29:11 +0000
From: "Luck, Tony" <tony.luck@...el.com>
To: "Yu, Fenghua" <fenghua.yu@...el.com>,
Ingo Molnar <mingo@...nel.org>
CC: Thomas Gleixner <tglx@...utronix.de>,
"Anvin, H Peter" <h.peter.anvin@...el.com>,
Ingo Molnar <mingo@...e.hu>, Borislav Petkov <bp@...e.de>,
Stephane Eranian <eranian@...gle.com>,
Peter Zijlstra <peterz@...radead.org>,
Vikas Shivappa <vikas.shivappa@...ux.intel.com>,
"Shankar, Ravi V" <ravi.v.shankar@...el.com>,
linux-kernel <linux-kernel@...r.kernel.org>, x86 <x86@...nel.org>
Subject: RE: [PATCH v2 2/3] Documentation, ABI: Add a document entry for
cache id
> It means one cache's id is unique in all caches with same cache index number.
> For example, in all caches with index3 (i.e. level3), cache id 0 is unique to identify
> a L3 cache. But in caches with index 0 (i.e. Level0), there is also a cache id 0.
> So cache id is unique in one index. But not unique in two different index.
> Does that make sense? I hope I express that correctly.
We use "index" rather than "level" because that is the terminology used
in /sys/devices/system/cpu/cpu*/cache/index*
E.g. on most Intel cpus you'll typically find "index0" is the L1-data cache,
"index1" is the L1-instruction cache, "index3" is the L2-unified cache and
"index4" is the L3-unified cache.
-Tony
Powered by blists - more mailing lists