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Message-ID: <3908561D78D1C84285E8C5FCA982C28F3A155BD7@ORSMSX114.amr.corp.intel.com>
Date:	Fri, 8 Jul 2016 18:47:33 +0000
From:	"Luck, Tony" <tony.luck@...el.com>
To:	Borislav Petkov <bp@...e.de>, Ingo Molnar <mingo@...nel.org>
CC:	"Yu, Fenghua" <fenghua.yu@...el.com>,
	Thomas Gleixner <tglx@...utronix.de>,
	"Anvin, H Peter" <h.peter.anvin@...el.com>,
	Ingo Molnar <mingo@...e.hu>,
	Stephane Eranian <eranian@...gle.com>,
	Peter Zijlstra <peterz@...radead.org>,
	Vikas Shivappa <vikas.shivappa@...ux.intel.com>,
	"Shankar, Ravi V" <ravi.v.shankar@...el.com>,
	linux-kernel <linux-kernel@...r.kernel.org>, x86 <x86@...nel.org>
Subject: RE: [PATCH v2 2/3] Documentation, ABI: Add a document entry for
 cache id

> > > "index4" is the L3-unified cache.
> > 
> > Crazy. What was wrong with using 'level' or 'depth'?
>
> It is all there:
>
> $ grep . /sys/devices/system/cpu/cpu0/cache/index?/level
> /sys/devices/system/cpu/cpu0/cache/index0/level:1

The term "index" came from the Intel Software developer manual, volume
2, description of CPUID instruction which talks about the index into leaf
and sub leaf.  I think Ingo might have been making a small dig at Intel
documentation :-)

-Tony
 

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