linux-kernel - [tip:x86/timers] x86/tsc_msr: Correct Silvermont reference clock values

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Message-ID: <tip-05680e7fa8a4e700e031a5e72cd8c18265f0031a@git.kernel.org>
Date:	Sun, 10 Jul 2016 11:11:36 -0700
From:	tip-bot for Len Brown <tipbot@...or.com>
To:	linux-tip-commits@...r.kernel.org
Cc:	hpa@...or.com, tglx@...utronix.de, torvalds@...ux-foundation.org,
	len.brown@...el.com, linux-kernel@...r.kernel.org,
	peterz@...radead.org, stephane.gasparini@...el.com,
	mingo@...nel.org
Subject: [tip:x86/timers] x86/tsc_msr: Correct Silvermont reference clock
 values

Commit-ID:  05680e7fa8a4e700e031a5e72cd8c18265f0031a
Gitweb:     http://git.kernel.org/tip/05680e7fa8a4e700e031a5e72cd8c18265f0031a
Author:     Len Brown <len.brown@...el.com>
AuthorDate: Fri, 17 Jun 2016 01:22:47 -0400
Committer:  Ingo Molnar <mingo@...nel.org>
CommitDate: Sun, 10 Jul 2016 17:00:13 +0200

x86/tsc_msr: Correct Silvermont reference clock values

Atom processors use a 19.2 MHz crystal oscillator.

Early processors generate 100 MHz via 19.2 MHz * 26 / 5 = 99.84 MHz.

Later preocessor generate 100 MHz via 19.2 MHz * 125 / 24 = 100 MHz.

Update the Silvermont-based tables accordingly,
matching the Software Developers Manual.

Also, correct a 166 MHz entry that should have been 116 MHz,
and add a missing 80 MHz entry.

Reported-by: Stephane Gasparini <stephane.gasparini@...el.com>
Signed-off-by: Len Brown <len.brown@...el.com>
Reviewed-by: Thomas Gleixner <tglx@...utronix.de>
Cc: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: Peter Zijlstra <peterz@...radead.org>
Link: http://lkml.kernel.org/r/5d7561655dfb066ff10801b423405bae4d1cfbe2.1466138954.git.len.brown@intel.com
Signed-off-by: Ingo Molnar <mingo@...nel.org>
---
 arch/x86/kernel/tsc_msr.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c
index 4110f72..20487e2 100644
--- a/arch/x86/kernel/tsc_msr.c
+++ b/arch/x86/kernel/tsc_msr.c
@@ -35,11 +35,11 @@ static struct freq_desc freq_desc_tables[] = {
 	/* CLV+ */
 	{ 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200 } },
 	/* TNG - Intel Atom processor Z3400 series */
-	{ 6, 0x4a, 1, { 0, 99840, 133200, 0, 0, 0, 0, 0 } },
+	{ 6, 0x4a, 1, { 0, 100000, 133300, 0, 0, 0, 0, 0 } },
 	/* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */
-	{ 6, 0x37, 1, { 83200, 99840, 133200, 166400, 0, 0, 0, 0 } },
+	{ 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0 } },
 	/* ANN - Intel Atom processor Z3500 series */
-	{ 6, 0x5a, 1, { 83200, 99840, 133200, 99840, 0, 0, 0, 0 } },
+	{ 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0 } },
 };
 
 static int match_cpu(u8 family, u8 model)