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Message-Id: <20160710193047.18320-3-nicstange@gmail.com>
Date: Sun, 10 Jul 2016 21:30:45 +0200
From: Nicolai Stange <nicstange@...il.com>
To: Thomas Gleixner <tglx@...utronix.de>
Cc: Ingo Molnar <mingo@...hat.com>, "H. Peter Anvin" <hpa@...or.com>,
x86@...nel.org, John Stultz <john.stultz@...aro.org>,
Borislav Petkov <bp@...e.de>,
Paolo Bonzini <pbonzini@...hat.com>,
Viresh Kumar <viresh.kumar@...aro.org>,
Hidehiro Kawai <hidehiro.kawai.ez@...achi.com>,
"Peter Zijlstra (Intel)" <peterz@...radead.org>,
"Christopher S. Hall" <christopher.s.hall@...el.com>,
Adrian Hunter <adrian.hunter@...el.com>,
linux-kernel@...r.kernel.org, Nicolai Stange <nicstange@...il.com>
Subject: [PATCH v2 2/4] arch, x86, tsc deadline clockevent dev: reduce TSC_DIVISOR to 2
In order to avoid overflowing an u32, the TSC deadline clockevent device's
frequency is divided by TSC_DIVISOR at registration.
The TSC_DIVISOR is currently defined as equaling 32 which allows for a
TSC frequency as high as 2^32 / 10^9ns * 32 = 137 GHz.
OTOH, larger values of TSC_DIVISOR introduce bigger roundoff errors into
the device's frequency.
A value of 2 for TSC_DIVISOR allows for a TSC frequency of
2^32 / 10^9ns * 2 = 8.5 GHz which is still way larger than anything to
expect in the next years.
Reduce the TSC deadline clockevent device's TSC_DIVISOR from 32 down to 2.
Signed-off-by: Nicolai Stange <nicstange@...il.com>
---
arch/x86/kernel/apic/apic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index dce654c..1d22c72 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -311,7 +311,7 @@ int lapic_get_maxlvt(void)
/* Clock divisor */
#define APIC_DIVISOR 16
-#define TSC_DIVISOR 32
+#define TSC_DIVISOR 2
/*
* This function sets up the local APIC timer, with a timeout of
--
2.9.0
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