| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <1468231899-6987-9-git-send-email-suravee.suthikulpanit@amd.com>
Date: Mon, 11 Jul 2016 05:11:36 -0500
From: Suravee Suthikulpanit <suravee.suthikulpanit@....com>
To: <joro@...tes.org>, <pbonzini@...hat.com>, <rkrcmar@...hat.com>,
<alex.williamson@...hat.com>
CC: <kvm@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<sherry.hurwitz@....com>,
Suravee Suthikulpanit <Suravee.Suthikulpanit@....com>
Subject: [PART2 PATCH v3 08/11] iommu/amd: Implements irq_set_vcpu_affinity() hook to setup vapic mode for pass-through devices
From: Suravee Suthikulpanit <Suravee.Suthikulpanit@....com>
This patch implements irq_set_vcpu_affinity() function to set up interrupt
remapping table entry with vapic mode for pass-through devices.
In case requirements for vapic mode are not met, it falls back to set up
the IRTE in legacy mode.
Signed-off-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@....com>
---
drivers/iommu/amd_iommu.c | 68 ++++++++++++++++++++++++++++++++++++++++++++---
include/linux/amd-iommu.h | 6 +++++
2 files changed, 70 insertions(+), 4 deletions(-)
diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c
index 95f106a..4abced5 100644
--- a/drivers/iommu/amd_iommu.c
+++ b/drivers/iommu/amd_iommu.c
@@ -3927,7 +3927,8 @@ out:
return index;
}
-static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte)
+static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
+ struct amd_ir_data *data)
{
struct irq_remap_table *table;
struct amd_iommu *iommu;
@@ -3953,6 +3954,8 @@ static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte)
entry->hi.fields.ga_root_ptr = tmp.hi.fields.ga_root_ptr;
entry->lo.val = irte->lo.val;
entry->lo.fields_remap.valid = 1;
+ if (data)
+ data->ref = entry;
spin_unlock_irqrestore(&table->lock, flags);
@@ -4051,7 +4054,7 @@ static void irte_ga_activate(void *entry, u16 devid, u16 index)
struct irte_ga *irte = (struct irte_ga *) entry;
irte->lo.fields_remap.valid = 1;
- modify_irte_ga(devid, index, irte);
+ modify_irte_ga(devid, index, irte, NULL);
}
static void irte_deactivate(void *entry, u16 devid, u16 index)
@@ -4067,7 +4070,7 @@ static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
struct irte_ga *irte = (struct irte_ga *) entry;
irte->lo.fields_remap.valid = 0;
- modify_irte_ga(devid, index, irte);
+ modify_irte_ga(devid, index, irte, NULL);
}
static void irte_set_affinity(void *entry, u16 devid, u16 index,
@@ -4088,7 +4091,7 @@ static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
irte->hi.fields.vector = vector;
irte->lo.fields_remap.destination = dest_apicid;
irte->lo.fields_remap.guest_mode = 0;
- modify_irte_ga(devid, index, irte);
+ modify_irte_ga(devid, index, irte, NULL);
}
#define IRTE_ALLOCATED (~1U)
@@ -4423,6 +4426,62 @@ static struct irq_domain_ops amd_ir_domain_ops = {
.deactivate = irq_remapping_deactivate,
};
+static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
+{
+ unsigned long flags;
+ struct amd_iommu *iommu;
+ struct amd_iommu_pi_data *pi_data = vcpu_info;
+ struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
+ struct amd_ir_data *ir_data = data->chip_data;
+ struct irte_ga *irte = (struct irte_ga *) ir_data->entry;
+ struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
+
+ /* Note:
+ * SVM tries to set up for VAPIC mode, but we are in
+ * legacy mode. So, we force legacy mode instead.
+ */
+ if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
+ pr_debug("AMD-Vi: %s: Fall back to using intr legacy remap\n",
+ __func__);
+ vcpu_pi_info = NULL;
+ }
+
+ iommu = amd_iommu_rlookup_table[irte_info->devid];
+ if (iommu == NULL)
+ return -EINVAL;
+
+ spin_lock_irqsave(&iommu->ga_hash_lock, flags);
+
+ if (vcpu_pi_info) {
+ /* Setting */
+ irte->hi.fields.vector = vcpu_pi_info->vector;
+ irte->lo.fields_vapic.guest_mode = 1;
+ irte->lo.fields_vapic.ga_tag =
+ AMD_IOMMU_GATAG(pi_data->avic_tag, pi_data->vcpu_id);
+
+ if (!hash_hashed(&ir_data->hnode))
+ hash_add(iommu->ga_hash, &ir_data->hnode,
+ (u16)(irte->lo.fields_vapic.ga_tag));
+ } else {
+ /* Un-Setting */
+ struct irq_cfg *cfg = irqd_cfg(data);
+
+ irte->hi.val = 0;
+ irte->lo.val = 0;
+ irte->hi.fields.vector = cfg->vector;
+ irte->lo.fields_remap.guest_mode = 0;
+ irte->lo.fields_remap.destination = cfg->dest_apicid;
+ irte->lo.fields_remap.int_type = apic->irq_delivery_mode;
+ irte->lo.fields_remap.dm = apic->irq_dest_mode;
+
+ hash_del(&ir_data->hnode);
+ }
+
+ spin_unlock_irqrestore(&iommu->ga_hash_lock, flags);
+
+ return modify_irte_ga(irte_info->devid, irte_info->index, irte, ir_data);
+}
+
static int amd_ir_set_affinity(struct irq_data *data,
const struct cpumask *mask, bool force)
{
@@ -4467,6 +4526,7 @@ static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
static struct irq_chip amd_ir_chip = {
.irq_ack = ir_ack_apic_edge,
.irq_set_affinity = amd_ir_set_affinity,
+ .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
.irq_compose_msi_msg = ir_compose_msi_msg,
};
diff --git a/include/linux/amd-iommu.h b/include/linux/amd-iommu.h
index 9897da8..46a893e 100644
--- a/include/linux/amd-iommu.h
+++ b/include/linux/amd-iommu.h
@@ -22,6 +22,12 @@
#include <linux/types.h>
+struct amd_iommu_pi_data {
+ u32 vcpu_id;
+ u32 avic_tag;
+ struct vcpu_data *vcpu_data;
+};
+
#ifdef CONFIG_AMD_IOMMU
struct task_struct;
--
1.9.1
Powered by blists - more mailing lists