lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Date:	Tue, 19 Jul 2016 06:45:18 -0700
From:	atull <atull@...nsource.altera.com>
To:	Moritz Fischer <moritz.fischer@...us.com>
CC:	Rob Herring <robh+dt@...nel.org>,
	Mark Rutland <mark.rutland@....com>,
	"Ian Campbell" <ijc+devicetree@...lion.org.uk>,
	Dinh Nguyen <dinguyen@...nsource.altera.com>,
	Devicetree List <devicetree@...r.kernel.org>,
	linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
	Alan Tull <delicious.quinoa@...il.com>
Subject: Re: [PATCH 1/2] ARM: socfpga: add bindings doc for arria10 fpga
 manager

On Sun, 17 Jul 2016, Moritz Fischer wrote:

> Acked-By: Moritz Fischer <moritz.fischer@...us.com>

Thanks Moritz!

Alan

> 
> On Tue, Jul 12, 2016 at 12:07 PM, Alan Tull <atull@...nsource.altera.com> wrote:
> > Add a device tree bindings document for the SoCFPGA Arria10
> > FPGA Manager driver.
> >
> > Signed-off-by: Alan Tull <atull@...nsource.altera.com>
> > ---
> >  .../bindings/fpga/altera-socfpga-a10-fpga-mgr.txt     | 19 +++++++++++++++++++
> >  1 file changed, 19 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
> >
> > diff --git a/Documentation/devicetree/bindings/fpga/altera-socfpga-a10-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
> > new file mode 100644
> > index 0000000..2fd8e7a
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
> > @@ -0,0 +1,19 @@
> > +Altera SOCFPGA Arria10 FPGA Manager
> > +
> > +Required properties:
> > +- compatible : should contain "altr,socfpga-a10-fpga-mgr"
> > +- reg        : base address and size for memory mapped io.
> > +               - The first index is for FPGA manager register access.
> > +               - The second index is for writing FPGA configuration data.
> > +- resets     : Phandle and reset specifier for the device's reset.
> > +- clocks     : Clocks used by the device.
> > +
> > +Example:
> > +
> > +       fpga_mgr: fpga-mgr@...03000 {
> > +               compatible = "altr,socfpga-a10-fpga-mgr";
> > +               reg = <0xffd03000 0x100
> > +                      0xffcfe400 0x20>;
> > +               clocks = <&l4_mp_clk>;
> > +               resets = <&rst FPGAMGR_RESET>;
> > +       };
> > --
> > 2.9.1
> >
> 

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ