linux-kernel - [PATCH 2/4] drm/mediatek: enhance the HDMI driving current

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Date:	Wed, 20 Jul 2016 12:03:03 +0800
From:	Bibby Hsieh <bibby.hsieh@...iatek.com>
To:	David Airlie <airlied@...ux.ie>,
	Matthias Brugger <matthias.bgg@...il.com>,
	Daniel Vetter <daniel.vetter@...ll.ch>,
	<dri-devel@...ts.freedesktop.org>,
	<linux-mediatek@...ts.infradead.org>
CC:	Yingjoe Chen <yingjoe.chen@...iatek.com>,
	Cawa Cheng <cawa.cheng@...iatek.com>,
	Daniel Kurtz <djkurtz@...omium.org>,
	Bibby Hsieh <bibby.hsieh@...iatek.com>,
	Philipp Zabel <p.zabel@...gutronix.de>,
	YT Shen <yt.shen@...iatek.com>,
	Thierry Reding <thierry.reding@...il.com>,
	CK Hu <ck.hu@...iatek.com>, Mao Huang <littlecvr@...omium.org>,
	<linux-arm-kernel@...ts.infradead.org>,
	<linux-kernel@...r.kernel.org>,
	Sascha Hauer <kernel@...gutronix.de>,
	Junzhi Zhao <junzhi.zhao@...iatek.com>
Subject: [PATCH 2/4] drm/mediatek: enhance the HDMI driving current

From: Junzhi Zhao <junzhi.zhao@...iatek.com>

In order to improve 4K resolution performance,
we have to enhance the HDMI driving currend
when clock rate is greater than 165MHz.

Signed-off-by: Junzhi Zhao <junzhi.zhao@...iatek.com>
Signed-off-by: Bibby Hsieh <bibby.hsieh@...iatek.com>
---
 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c |   89 +++++++++++++++++-------
 1 file changed, 63 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
index 8a24754..a871c14 100644
--- a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
+++ b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
@@ -298,32 +298,69 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 			  (0x1 << PLL_BR_SHIFT),
 			  RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC |
 			  RG_HDMITX_PLL_BR);
-	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, RG_HDMITX_PRD_IMP_EN);
-	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4,
-			  (0x3 << PRD_IBIAS_CLK_SHIFT) |
-			  (0x3 << PRD_IBIAS_D2_SHIFT) |
-			  (0x3 << PRD_IBIAS_D1_SHIFT) |
-			  (0x3 << PRD_IBIAS_D0_SHIFT),
-			  RG_HDMITX_PRD_IBIAS_CLK |
-			  RG_HDMITX_PRD_IBIAS_D2 |
-			  RG_HDMITX_PRD_IBIAS_D1 |
-			  RG_HDMITX_PRD_IBIAS_D0);
-	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3,
-			  (0x0 << DRV_IMP_EN_SHIFT), RG_HDMITX_DRV_IMP_EN);
-	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6,
-			  (hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) |
-			  (hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) |
-			  (hdmi_phy->drv_imp_d1 << DRV_IMP_D1_SHIFT) |
-			  (hdmi_phy->drv_imp_d0 << DRV_IMP_D0_SHIFT),
-			  RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 |
-			  RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0);
-	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5,
-			  (hdmi_phy->ibias << DRV_IBIAS_CLK_SHIFT) |
-			  (hdmi_phy->ibias << DRV_IBIAS_D2_SHIFT) |
-			  (hdmi_phy->ibias << DRV_IBIAS_D1_SHIFT) |
-			  (hdmi_phy->ibias << DRV_IBIAS_D0_SHIFT),
-			  RG_HDMITX_DRV_IBIAS_CLK | RG_HDMITX_DRV_IBIAS_D2 |
-			  RG_HDMITX_DRV_IBIAS_D1 | RG_HDMITX_DRV_IBIAS_D0);
+	if (rate < 165000000) {
+		mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3,
+					RG_HDMITX_PRD_IMP_EN);
+		mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4,
+				  (0x3 << PRD_IBIAS_CLK_SHIFT) |
+				  (0x3 << PRD_IBIAS_D2_SHIFT) |
+				  (0x3 << PRD_IBIAS_D1_SHIFT) |
+				  (0x3 << PRD_IBIAS_D0_SHIFT),
+				  RG_HDMITX_PRD_IBIAS_CLK |
+				  RG_HDMITX_PRD_IBIAS_D2 |
+				  RG_HDMITX_PRD_IBIAS_D1 |
+				  RG_HDMITX_PRD_IBIAS_D0);
+		mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3,
+				  (0x0 << DRV_IMP_EN_SHIFT),
+				  RG_HDMITX_DRV_IMP_EN);
+		mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6,
+				  (hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) |
+				  (hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) |
+				  (hdmi_phy->drv_imp_d1 << DRV_IMP_D1_SHIFT) |
+				  (hdmi_phy->drv_imp_d0 << DRV_IMP_D0_SHIFT),
+				  RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 |
+				  RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0);
+		mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5,
+				  (hdmi_phy->ibias << DRV_IBIAS_CLK_SHIFT) |
+				  (hdmi_phy->ibias << DRV_IBIAS_D2_SHIFT) |
+				  (hdmi_phy->ibias << DRV_IBIAS_D1_SHIFT) |
+				  (hdmi_phy->ibias << DRV_IBIAS_D0_SHIFT),
+				  RG_HDMITX_DRV_IBIAS_CLK |
+				  RG_HDMITX_DRV_IBIAS_D2 |
+				  RG_HDMITX_DRV_IBIAS_D1 |
+				  RG_HDMITX_DRV_IBIAS_D0);
+	} else {
+		mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3,
+				      RG_HDMITX_PRD_IMP_EN);
+		mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4,
+				  (0x6 << PRD_IBIAS_CLK_SHIFT) |
+				  (0x6 << PRD_IBIAS_D2_SHIFT) |
+				  (0x6 << PRD_IBIAS_D1_SHIFT) |
+				  (0x6 << PRD_IBIAS_D0_SHIFT),
+				  RG_HDMITX_PRD_IBIAS_CLK |
+				  RG_HDMITX_PRD_IBIAS_D2 |
+				  RG_HDMITX_PRD_IBIAS_D1 |
+				  RG_HDMITX_PRD_IBIAS_D0);
+		mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3,
+				  (0xf << DRV_IMP_EN_SHIFT),
+				  RG_HDMITX_DRV_IMP_EN);
+		mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6,
+				  (hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) |
+				  (hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) |
+				  (hdmi_phy->drv_imp_d1 << DRV_IMP_D1_SHIFT) |
+				  (hdmi_phy->drv_imp_d0 << DRV_IMP_D0_SHIFT),
+				  RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 |
+				  RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0);
+		mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5,
+				  (hdmi_phy->ibias_up << DRV_IBIAS_CLK_SHIFT) |
+				  (hdmi_phy->ibias_up << DRV_IBIAS_D2_SHIFT) |
+				  (hdmi_phy->ibias_up << DRV_IBIAS_D1_SHIFT) |
+				  (hdmi_phy->ibias_up << DRV_IBIAS_D0_SHIFT),
+				  RG_HDMITX_DRV_IBIAS_CLK |
+				  RG_HDMITX_DRV_IBIAS_D2 |
+				  RG_HDMITX_DRV_IBIAS_D1 |
+				  RG_HDMITX_DRV_IBIAS_D0);
+	}
 	return 0;
 }
 
-- 
1.7.9.5