linux-kernel - Re: [PATCH 2/2] PCI: designware: let dw_pcie_link

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <c79de6c7-5d86-4090-085b-63163d2467e7@synopsys.com>
Date:	Thu, 21 Jul 2016 11:11:23 +0100
From:	Joao Pinto <Joao.Pinto@...opsys.com>
To:	Jisheng Zhang <jszhang@...vell.com>,
	Joao Pinto <Joao.Pinto@...opsys.com>
CC:	<jingoohan1@...il.com>, <pratyush.anand@...il.com>,
	<bhelgaas@...gle.com>, <linux-pci@...r.kernel.org>,
	<linux-kernel@...r.kernel.org>,
	<linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH 2/2] PCI: designware: let dw_pcie_link_up() beware of
 LTSSM training bit


Hi Jisheng,

On 7/18/2016 3:38 AM, Jisheng Zhang wrote:
> Dear Joao,
> 
> On Fri, 15 Jul 2016 16:10:24 +0100 Joao Pinto wrote:
> 
>> Hi,
>>
>> On 7/6/2016 11:59 AM, Jisheng Zhang wrote:
>>> The link may be UP but still in link training. In this case, we can't
>>> think the link is up and operating correctly. So we need to teach
>>> dw_pcie_link_up() beware of the PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING bit.
>>>
>>> This patch also rewrite PCIE_PHY_DEBUG_R1_LINK_UP definition so that
>>> it's consistent with other MACROS.
>>>
>>> Signed-off-by: Jisheng Zhang <jszhang@...vell.com>
>>> ---
>>>  drivers/pci/host/pcie-designware.c | 6 ++++--
>>>  1 file changed, 4 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
>>> index 9df879a..29e10dd 100644
>>> --- a/drivers/pci/host/pcie-designware.c
>>> +++ b/drivers/pci/host/pcie-designware.c
>>> @@ -73,7 +73,8 @@
>>>  /* PCIe Port Logic registers */
>>>  #define PLR_OFFSET			0x700
>>>  #define PCIE_PHY_DEBUG_R1		(PLR_OFFSET + 0x2c)
>>> -#define PCIE_PHY_DEBUG_R1_LINK_UP	0x00000010
>>> +#define PCIE_PHY_DEBUG_R1_LINK_UP	(0x1 << 4)
>>> +#define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING	(0x1 << 29)  
>>
>> According to the databook bit 29 is inside a range that is dedicated to M-PCIe.
>> Have you checked bit 29 state by experience?
> 
> bit 29 here is bit 61 of cxpl_debug_info(64bit) in databook, the debug info is
> composited by debug 0 and debug 1 registers.

You are absolutely correct... I misread the databook in this subject.
In the latest Core versions this is also valid.

Acked-By: Joao Pinto <jpinto@...opsys.com>