linux-kernel - Re: [PATCH v3 1/3] arm64: mm: add __clean_dcache

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Message-ID: <20160721161137.GG21616@arm.com>
Date:	Thu, 21 Jul 2016 17:11:37 +0100
From:	Will Deacon <will.deacon@....com>
To:	Kwangwoo Lee <kwangwoo.lee@...com>
Cc:	linux-arm-kernel@...ts.infradead.org, linux-nvdimm@...ts.01.org,
	Catalin Marinas <catalin.marinas@....com>,
	Mark Rutland <mark.rutland@....com>,
	Ross Zwisler <ross.zwisler@...ux.intel.com>,
	Dan Williams <dan.j.williams@...el.com>,
	Vishal Verma <vishal.l.verma@...el.com>,
	Woosuk Chung <woosuk.chung@...com>,
	Hyunchul Kim <hyunchul3.kim@...com>,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 1/3] arm64: mm: add __clean_dcache_area()

On Fri, Jul 15, 2016 at 11:46:20AM +0900, Kwangwoo Lee wrote:
> Ensure D-cache lines are cleaned to the PoC(Point of Coherency).
> 
> This function is called by arch_wb_cache_pmem() to clean the cache lines
> and remain the data in cache for the next access.
> 
> Signed-off-by: Kwangwoo Lee <kwangwoo.lee@...com>
> ---
>  arch/arm64/include/asm/cacheflush.h |  1 +
>  arch/arm64/mm/cache.S               | 18 ++++++++++++++++++
>  2 files changed, 19 insertions(+)
> 
> diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/cacheflush.h
> index c64268d..903a94f 100644
> --- a/arch/arm64/include/asm/cacheflush.h
> +++ b/arch/arm64/include/asm/cacheflush.h
> @@ -68,6 +68,7 @@
>  extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
>  extern void flush_icache_range(unsigned long start, unsigned long end);
>  extern void __flush_dcache_area(void *addr, size_t len);
> +extern void __clean_dcache_area(void *addr, size_t len);
>  extern void __clean_dcache_area_pou(void *addr, size_t len);
>  extern long __flush_cache_user_range(unsigned long start, unsigned long end);
>  
> diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S
> index 6df0706..5a350e4 100644
> --- a/arch/arm64/mm/cache.S
> +++ b/arch/arm64/mm/cache.S
> @@ -93,6 +93,24 @@ ENTRY(__flush_dcache_area)
>  ENDPIPROC(__flush_dcache_area)
>  
>  /*
> + *	__clean_dcache_area(kaddr, size)
> + *
> + * 	Ensure that any D-cache lines for the interval [kaddr, kaddr+size)
> + * 	are cleaned to the PoC.
> + *
> + *	- kaddr   - kernel address
> + *	- size    - size in question
> + */
> +ENTRY(__clean_dcache_area)
> +alternative_if_not ARM64_WORKAROUND_CLEAN_CACHE
> +	dcache_by_line_op cvac, sy, x0, x1, x2, x3
> +alternative_else
> +	dcache_by_line_op civac, sy, x0, x1, x2, x3
> +alternative_endif
> +	ret
> +ENDPROC(__clean_dcache_area)

This looks functionally equivalent to __dma_clean_range. How about we:

  1. Convert the __dma_* routines to use dcache_by_line
  2. Introduce __clean_dcache_area_poc as a fallthrough to __dma_clean_range
  3. Use __clean_dcache_area_poc for the pmem stuff (with some parameter
     marshalling in the macro).

Will