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Message-ID: <CACbG30_1hTRpaNb+vwb79JW=J4y+WTh5YiT-nPo2kMypnr-Trg@mail.gmail.com>
Date:	Tue, 26 Jul 2016 14:00:35 -0500
From:	Nilay Vaish <nilayvaish@...il.com>
To:	Fenghua Yu <fenghua.yu@...el.com>
Cc:	Thomas Gleixner <tglx@...utronix.de>, Ingo Molnar <mingo@...e.hu>,
	"H. Peter Anvin" <h.peter.anvin@...el.com>,
	Tony Luck <tony.luck@...el.com>, Tejun Heo <tj@...nel.org>,
	Borislav Petkov <bp@...e.de>,
	Stephane Eranian <eranian@...gle.com>,
	Peter Zijlstra <peterz@...radead.org>,
	Marcelo Tosatti <mtosatti@...hat.com>,
	David Carrillo-Cisneros <davidcc@...gle.com>,
	Ravi V Shankar <ravi.v.shankar@...el.com>,
	Vikas Shivappa <vikas.shivappa@...ux.intel.com>,
	Sai Prakhya <sai.praneeth.prakhya@...el.com>,
	linux-kernel <linux-kernel@...r.kernel.org>, x86 <x86@...nel.org>
Subject: Re: [PATCH 02/32] x86/intel_rdt: Add support for Cache Allocation detection

On 12 July 2016 at 20:02, Fenghua Yu <fenghua.yu@...el.com> wrote:
> diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
> index 0fe6953..42c90cb 100644
> --- a/arch/x86/kernel/cpu/common.c
> +++ b/arch/x86/kernel/cpu/common.c
> @@ -711,6 +711,21 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
>                 }
>         }
>
> +       /* Additional Intel-defined flags: level 0x00000010 */
> +       if (c->cpuid_level >= 0x00000010) {
> +               u32 eax, ebx, ecx, edx;
> +
> +               cpuid_count(0x00000010, 0, &eax, &ebx, &ecx, &edx);
> +               c->x86_capability[14] = ebx;

Should we have a name for this capability / leaf, instead of that
constant 14?  grep informs me that everywhere else we use enum of type
cpuid_leafs.


--
Nilay

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