linux-kernel - Re: [PATCH 10/32] x86/intel_rdt: Adds support to enable Code Data Prioritization

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Message-ID: <alpine.DEB.2.10.1607261329360.4760@vshiva-Udesk>
Date:	Tue, 26 Jul 2016 13:32:05 -0700 (PDT)
From:	Shivappa Vikas <vikas.shivappa@...ux.intel.com>
To:	Nilay Vaish <nilayvaish@...il.com>
cc:	Fenghua Yu <fenghua.yu@...el.com>,
	Thomas Gleixner <tglx@...utronix.de>,
	Ingo Molnar <mingo@...e.hu>,
	"H. Peter Anvin" <h.peter.anvin@...el.com>,
	Tony Luck <tony.luck@...el.com>, Tejun Heo <tj@...nel.org>,
	Borislav Petkov <bp@...e.de>,
	Stephane Eranian <eranian@...gle.com>,
	Peter Zijlstra <peterz@...radead.org>,
	Marcelo Tosatti <mtosatti@...hat.com>,
	David Carrillo-Cisneros <davidcc@...gle.com>,
	Ravi V Shankar <ravi.v.shankar@...el.com>,
	Vikas Shivappa <vikas.shivappa@...ux.intel.com>,
	Sai Prakhya <sai.praneeth.prakhya@...el.com>,
	linux-kernel <linux-kernel@...r.kernel.org>, x86 <x86@...nel.org>
Subject: Re: [PATCH 10/32] x86/intel_rdt: Adds support to enable Code Data
 Prioritization



On Tue, 26 Jul 2016, Nilay Vaish wrote:

> On 12 July 2016 at 20:02, Fenghua Yu <fenghua.yu@...el.com> wrote:
>> From: Vikas Shivappa <vikas.shivappa@...ux.intel.com>
>>
>> On Intel SKUs that support Code Data Prioritization(CDP), intel_rdt
>> operates in 2 modes - legacy cache allocation mode/default or CDP mode.
>>
>> When CDP is enabled, the number of available CLOSids is halved. Hence the
>> enabling is done when less than half the number of CLOSids available are
>> used. When CDP is enabled each CLOSid maps to a
>> data cache mask and an instruction cache mask. The enabling itself is done
>> by writing to the IA32_PQOS_CFG MSR and can dynamically be enabled or
>> disabled.
>>
>> CDP is disabled when for each (dcache_cbm,icache_cbm) pair, the
>> dcache_cbm = icache_cbm.
>>
>> Signed-off-by: Vikas Shivappa <vikas.shivappa@...ux.intel.com>
>> Signed-off-by: Fenghua Yu <fenghua.yu@...el.com>
>> Reviewed-by: Tony Luck <tony.luck@...el.com>
>> ---
>>  arch/x86/include/asm/intel_rdt.h |  7 +++++
>>  arch/x86/kernel/cpu/intel_rdt.c  | 66 ++++++++++++++++++++++++++--------------
>>  2 files changed, 51 insertions(+), 22 deletions(-)
>>
>> diff --git a/arch/x86/include/asm/intel_rdt.h b/arch/x86/include/asm/intel_rdt.h
>> index 6e20314..f2cb91d 100644
>> --- a/arch/x86/include/asm/intel_rdt.h
>> +++ b/arch/x86/include/asm/intel_rdt.h
>> @@ -8,6 +8,7 @@
>>  #define MAX_CBM_LENGTH                 32
>>  #define IA32_L3_CBM_BASE               0xc90
>>  #define CBM_FROM_INDEX(x)              (IA32_L3_CBM_BASE + x)
>> +#define MSR_IA32_PQOS_CFG              0xc81
>>
>>  extern struct static_key rdt_enable_key;
>>  void __intel_rdt_sched_in(void *dummy);
>> @@ -17,6 +18,12 @@ struct clos_cbm_table {
>>         unsigned int clos_refcnt;
>>  };
>>
>> +struct clos_config {
>> +       unsigned long *closmap;
>> +       u32 max_closid;
>> +       u32 closids_used;
>> +};
>> +
>
> I think most of this patch is not about CDP, but about moving from an
> independently defined closmap to one defined as part of struct
> clos_config.  I suggest we combine part of this patch with patch 03/32
> and work with struct clos_config right from the beginning.

Its moved to struct to track the number of closids used as the cdp mode can be 
switched only when half the number of closids. it has other updates like 
using the cctable as its not indexed by raw closid but depends on whether closid 
is used for data or i cache

Thanks,
Vikas

>
>
> Thanks
> Nilay
>